CDCV857A

2.5-V PHASE LOCK LOOP CLOCK DRIVER

SCAS667A – APRIL 2001 – REVISED AUGUST 2002

1

POST OFFICE BOX 655303

Data-Rate Synchronous DRAM

Applications

Ten Differential Outputs

Differential Clocks Are <20 MHz

56-Ball MicroStar Junior

 BGA Package

Used to Synchronize the Outputs to the

Input Clocks

description

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock

input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback

clock output (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback

and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-state),

and the PLL is shut down (low power mode). The device also enters this low power mode when the input

frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input

frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this

detection circuit turns on the PLL again and enables the outputs.

to track spread spectrum clocking for reduced EMI.

Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up. The CDCV857A is characterized for operation from 0

°C

to 85

°C.

Copyright

 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior is a trademark of Texas Instruments Incorporated.