Datenblatt-Suchmaschine für elektronische Bauteile |
|
ADSP-BF532SBST400 Datenblatt(PDF) 10 Page - Analog Devices |
|
ADSP-BF532SBST400 Datenblatt(HTML) 10 Page - Analog Devices |
10 / 56 page Rev. 0 | Page 10 of 56 | March 2004 ADSP-BF531/ADSP-BF532/ADSP-BF533 During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. UART PORT The ADSP-BF531/2/3 processor provides a full-duplex Univer- sal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART port includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (Programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (Direct Memory Access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port's baud rate, serial data format, error code gen- eration and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. • Supporting data formats from 7 to12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. The UART port’s clock rate is calculated as: Where the 16-bit UART_Divisor comes from the DLH register (most significant 8 bits) and DLL register (least significant 8bits). In conjunction with the general-purpose timer functions, auto- baud detection is supported. The capabilities of the UART are further extended with support for the Infrared Data Association (IrDA®) Serial Infrared Physi- cal Layer Link Specification (SIR) protocol. PROGRAMMABLE FLAGS (PFX) The ADSP-BF531/2/3 processor has 16 bidirectional, general- purpose Programmable Flag (PF15–0) pins. Each programma- ble flag can be individually controlled by manipulation of the flag control, status and interrupt registers: • Flag Direction Control Register – Specifies the direction of each individual PFx pin as input or output. • Flag Control and Status Registers – The ADSP-BF531/2/3 processor employs a “write one to modify” mechanism that allows any combination of individual flags to be modified in a single instruction, without affecting the level of any other flags. Four control registers are provided. One regis- ter is written in order to set flag values, one register is written in order to clear flag values, one register is written in order to toggle flag values, and one register is written in order to specify a flag value. Reading the flag status register allows software to interrogate the sense of the flags. • Flag Interrupt Mask Registers – The two Flag Interrupt Mask Registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two Flag Con- trol Registers that are used to set and clear individual flag values, one Flag Interrupt Mask Register sets bits to enable interrupt function, and the other Flag Interrupt Mask reg- ister clears bits to disable interrupt function. PFx pins defined as inputs can be configured to generate hardware interrupts, while output PFx pins can be triggered by soft- ware interrupts. • Flag Interrupt Sensitivity Registers – The two Flag Inter- rupt Sensitivity Registers specify whether individual PFx pins are level- or edge-sensitive and specify—if edge-sensi- tive—whether just the rising edge or both the rising and falling edges of the signal are significant. One register selects the type of sensitivity, and one register selects which edges are significant for edge-sensitivity. PARALLEL PERIPHERAL INTERFACE The processor provides a Parallel Peripheral Interface (PPI) that can connect directly to parallel A/D and D/A converters, ITU-R 601/656 video encoders and decoders, and other general-pur- pose peripherals. The PPI consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. The input clock supports parallel data rates up to half the system clock rate. In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported. Three distinct ITU-R 656 modes are supported: • Active Video Only - The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during UART Clock Rate fSCLK 16 UART_Divisor × ------------------------------------------------ = |
Ähnliche Teilenummer - ADSP-BF532SBST400 |
|
Ähnliche Beschreibung - ADSP-BF532SBST400 |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |