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LM2512A Datenblatt(PDF) 5 Page - Texas Instruments |
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LM2512A Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 28 page LM2512A www.ti.com SNLS269B – AUGUST 2007 – REVISED MAY 2013 SWITCHING CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol Parameter Conditions Min Typ Max Units tACC SPI Data Active (SDA_device) See Figure 16 0 50 ns tOHR SPI Data Tri-State 0 50 ns (SDA_device) RECOMMENDED INPUT TIMING REQUIREMENTS (PCLK AND SPI) Over recommended operating supply and temperature ranges unless otherwise specified. (1) Symbol Parameter Conditions Min Typ Max Units PIXEL CLOCK (PCLK) fPCLK Pixel Clock Frequency 3 MD Lane, (4X) 7.5 22.5 MHz 2 MD Lane, (6X) 5 15 MHz PCLKDC Pixel Clock Duty Cycle 30 50 70 % tT Transition Time See(2)(3) 2 >2 ns tSTOPpclk Clock Stop Gap PCLK See(4) (3) 4 2 cycles SPI INTERFACE fSCLw SCL Frequency WRITE 10 MHz fSCLr READ 6.67 MHz ts0 CSX Set Time 60 ns ts1 SI Set Time See Figure 15 30 ns th1 SI Hold Time 30 ns tw1h SCL Pulse Width High WRITE 35 ns READ 60 ns See Figure 15, Figure 16 tw1l SCL Pulse Width Low WRITE 35 ns READ 60 ns tr SCL Rise Time 5 ns tf SCL Fall Time 5 ns t0H SI Hold Time See Figure 15 30 ns th0 CSX Hold Time 65 ns tw2 CSX OFF Time 100 ns (1) Typical values are given for VDDIO = 1.8V and VDD = VDDA = 1.8V and TA = 25°C. (2) Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality. (3) This is a functional parameter and is specified by design or characterization. (4) This is the minimum time that the PCLK needs to be held off for in order for the device to be reset. Once PCLK is reapplied, a PLL Lock is required and start up sequence before video data is serialized. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM2512A |
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