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DP83934CVUL-20 Datenblatt(PDF) 69 Page - National Semiconductor (TI) |
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DP83934CVUL-20 Datenblatt(HTML) 69 Page - National Semiconductor (TI) |
69 / 104 page 70 Bus Interface (Continued) 7372 Slave Cycle for BMODE e 0 The system accesses the SONIC-T by driving SAS CS SWR and RAk50l These signals will be sampled each bus cycle but the SONIC-T will not actually start a slave cycle until CS has been sampled low and SAS has been sampled high CS should not be asserted low before the falling edge of SAS as this will cause improper slave opera- tion CS may be asserted low however before the rising edge of SAS In this case it is suggested that SAS be driven high within one bus clock after the falling edge of CS Be- tween one and two bus clocks after the assertion of CS once SAS has been driven high SMACK will be driven low to signify that the SONIC-T has started the slave cycle Al- though CS is an asynchronous input meeting its setup time (as shown in Figures 7-21 and 7-22 ) will guarantee that SMACK which is asserted off a falling edge will be assert- ed 1 bus clock after the falling edge that CS was clocked in on This is assuming that the SONIC-T is not a bus master when CS is asserted If the SONIC-T is a bus master then when CS is asserted the SONIC-T will complete its current master bus cycle and get off the bus temporarily (see Sec- tion 738) In this case SMACK will be asserted 5 bus clocks after the falling edge that CS was clocked in on This is assuming that there were no wait states in the current master mode access Wait states will increase the time for SMACK to go low by the number of wait states in the cycle If the slave access is a read cycle (Figure 7-21) then the data will be driven off the same edge as SMACK Ifitisa write cycle (Figure 7-22) then the data will be latched in exactly 2 bus clocks after the assertion of SMACK In either case RDYo is driven low 25 bus clocks after SMACK to terminate the slave cycle For a read cycle the assertion of RDYo indicates valid register data and for a write cycle the assertion indicates that the SONIC-T has latched the data The SONIC-T deasserts RDYi SMACK and the data if the cycle is a read cycle at the falling edge of SAS or the rising edge of CS depending on which is first Note 1 The SONIC-T transfers data only on lines Dk150l during slave mode accesses Note 2 For multiple register accesses CS can be held low and SAS can be used to delimit the slave cycle (this is the only case where CS may be asserted before SAS) In this case SMACK will be driven low due to SAS going high since CS has already been asserted Notice that this means SMACK will not stay asserted low during the entire time CS is low (as is the case for MREQ Section 738) Note 3 If memory request (MREQ) follows a chip select CS it must be asserted at least 2 bus clocks after CS is deasserted Both CS and MREQ must not be asserted concurrently Note 4 When CS is deasserted it must remain deasserted for at least one bus clock Note 5 The way in which SMACK is asserted due to CS is not the same as the way in which SMACK is asserted due to MREQ The assertion of SMACK is dependent upon both CS and SAS being low not just CS This is not the same as the case for MREQ (see Section 738) The assertion of SMACK in these two cases should not be confused TLF11719 – 48 FIGURE 7-21 Register Read BMODE e 0 69 |
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