LM2619

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SNVS212B – NOVEMBER 2002 – REVISED MAY 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)

PVIN, VDD to SGND

−0.2V to +6V

PGND to SGND, PVIN to VDD

−0.2V to +0.2V

EN, EAOUT, EANEG, SYNC/MODE to SGND

−0.2V to +6V

FB, SW

(GND

−0.2V) to (VDD +0.2V)

Storage temperature range

−45°C to +150°C

Lead temperature (soldering, 10 sec.)

260°C

−25°C to +125°C

Minimum ESD rating (Human Body Model, C = 100 pF, R = 1.5 k

Ω)

±2 kV

Thermal resistance (

(3)

140°C/W

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional. For specifications and associated test conditions, see the Min and Max limits and Conditions in the

Electrical Characteristics table. Typical (typ) specifications are mean or average values at 25°C.

(2)

Thermal shutdown will occur if the junction temperature exceeds 150°C.

(3)

Thermal resistance specified with 2 layer PCB (0.5/0.5 oz. cu).

Electrical Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input voltage range

(1)

2.8

3.6

5.5

V

Feedback voltage

1.485

1.50

1.515

V

PFM comparator hysteresis voltage

24

mV

Shutdown supply current

VIN = 3.6V, EN = 0V

0.02

3

µA

DC bias current into VDD

SYNC/MODE = VIN, FB = 2V

600

725

µA

SYNC/MODE = 0V, FB = 2V

160

195

µA

Pin-pin resistance for PFET

395

550

m

Ω

Pin-pin resistance for NFET

330

500

m

Ω

FET resistance temperature coefficient

0.5

%/C

620

810

1100

mA

Logic high input, EN, SYNC/MODE

0.95

1.3

V

Logic low input, EN, SYNC/MODE

0.4

0.80

V

SYNC/MODE clock frequency range

(4)

500

1000

kHz

Internal oscillator frequency

PWM Mode

468

600

732

kHz

Minimum on-time of PFET switch in

200

ns

PWM mode

(1)

The LM2619 is designed for mobile phone applications where turn-on after system power-up is controlled by the system controller.

Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.8V.

(2)

The hysteresis voltage is the minimum voltage swing on the FB pin that causes the internal feedback and control circuitry to turn the

internal PFET switch on and then off during PFM mode. When resistor dividers are used like in the operating circuit of Figure 20, the

hysteresis at the output will be the value of the hysteresis at the feedback pin times the resistor divider ratio. In this case, 24mV (typ) x

((46.4k + 33.2k)/33.2k).

(3)

Current limit is built-in, fixed, and not adjustable. If the current limit is reached while the voltage at the FB pin is pulled below 0.7V, the

internal PFET switch turns off for 2.5µs to allow the inductor current to diminish.

(4)

in PWM mode at the external clock frequency. The LM2619 synchronizes to the rising edge of the external clock.

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