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SN74ABT3613-30PCB Datenblatt(PDF) 5 Page - Texas Instruments

Teilenummer SN74ABT3613-30PCB
Bauteilbeschribung  CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING
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SN74ABT3613-30PCB Datenblatt(HTML) 5 Page - Texas Instruments

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SN74ABT3613
64
× 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SCBS128F – JULY 1992 – REVISED APRIL 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
A0–A35
I/O
Port-A data. The 36-bit bidirectional data port for side A.
AE
O
(port B)
Almost-empty flag. Programmable almost-empty flag synchronized to CLKB. AE is low when the number of 36-bit
words in the FIFO is less than or equal to the value in offset register X.
AF
O
(port A)
Almost-full flag. Programmable almost-full flag synchronized to CLKA. AF is low when the number of 36-bit empty
locations in the FIFO is less than or equal to the value in offset register X.
B0–B35
I/O
Port-B data. The 36-bit bidirectional data port for side B.
BE
I
Big-endian select. Selects the bytes on port B used during byte or word FIFO reads. A low on BE selects the
most-significant bytes on B0–B35 for use, and a high selects the least-significant bytes.
CLKA
I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. FF and AF are synchronized to the low-to-high transition of CLKA.
CLKB
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. Port-B byte swapping and data-port-sizing operations are also synchronous
to the low-to-high transition of CLKB. EF and AE are synchronized to the low-to-high transition of CLKB.
CSA
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA is high.
CSB
I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB is high.
EF
O
(port B)
Empty flag. EF is synchronized to the low-to-high transition of CLKB. When EF is low, the FIFO is empty and reads
from its memory are disabled. Data can be read from the FIFO to the output register when EF is high. EF is forced
low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into
empty FIFO memory.
ENA
I
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB
I
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FF
O
(port A)
Full flag. FF is synchronized to the low-to-high transition of CLKA. When FF is low, the FIFO is full and writes to its
memory are disabled. FF is forced low when the device is reset and is set high by the second low-to-high transition
of CLKA after reset.
FS1
FS0
I
Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the AE flag and AF flag offset.
MBA
I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When
the A0–A35 outputs are active, mail2 register data is output.
MBF1
O
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a
port-B read is selected and both SIZ1 and SIZ0 are high. MBF1 is set high when the device is reset.
MBF2
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a
port-A read is selected and MBA is high. MBF2 is set high when the device is reset.
ODD/EVEN
I
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
PEFA
O
(port A)
Port-A parity error flag. When any byte applied to terminals A0–A35 fails parity, PEFA is low. Bytes are organized
as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The
type of parity checked is determined by the state of ODD/EVEN.
The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity
generation is selected by PGA; therefore, if a mail2 read with parity generation is set up by having CSA low, ENA
high, W/RA low, MBA high, and PGA high, the PEFA flag is forced high, regardless of the state of the A0–A35 inputs.


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