Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

SN74GTLP1394 Datenblatt(PDF) 2 Page - Texas Instruments

Teilenummer SN74GTLP1394
Bauteilbeschribung  2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
Download  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74GTLP1394 Datenblatt(HTML) 2 Page - Texas Instruments

  SN74GTLP1394_15 Datasheet HTML 1Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 2Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 3Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 4Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 5Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 6Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 7Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 8Page - Texas Instruments SN74GTLP1394_15 Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 23 page
background image
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
FUNCTIONAL DESCRIPTION
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2005
The SN74GTLP1394 is a high-drive, 2-bit, 3-wire bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data transfer
with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and diagnostics
monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a
backplane operating at GTLP signal levels, and is especially designed to work with the Texas Instruments (TI™)
1394 backplane physical-layer controllers. High-speed (about three times faster than standard LVTTL or TTL)
backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels,
improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry
minimizes bus-settling time and have been designed and tested using several backplane models. The high drive
allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11
Ω.
GTLP is the TI derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac
specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTLP, but the user has
the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and
VREF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal and permits
true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and V
CC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When V
CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
The output-enable (OEAB) input controls the activity of the B port. When OEAB is low, the B-port outputs are
active. When OEAB is high, the B-port outputs are disabled.
Separate LVTTL input and output pins provide a feedback path for control and diagnostics monitoring. The
OEBY input controls the Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the Y
outputs are disabled.
The polarity-control (T/C) input is provided to select polarity of data transmission in both directions. When T/C is
high, data transmission is true, and A data goes to the B bus and B data goes to the Y bus. When T/C is low,
data transmission is complementary, and inverted A data goes to the B bus and inverted B data goes to the Y
bus.
2


Ähnliche Teilenummer - SN74GTLP1394_15

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Texas Instruments
SN74GTLP1394D TI-SN74GTLP1394D Datasheet
143Kb / 9P
[Old version datasheet]   2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394D TI-SN74GTLP1394D Datasheet
741Kb / 25P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1394DGV TI-SN74GTLP1394DGV Datasheet
143Kb / 9P
[Old version datasheet]   2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394DGVR TI-SN74GTLP1394DGVR Datasheet
741Kb / 25P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1394DR TI-SN74GTLP1394DR Datasheet
741Kb / 25P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
More results

Ähnliche Beschreibung - SN74GTLP1394_15

HerstellerTeilenummerDatenblattBauteilbeschribung
logo
Texas Instruments
SN74GTLP1394 TI-SN74GTLP1394_07 Datasheet
741Kb / 25P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1395 TI-SN74GTLP1395 Datasheet
443Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP21395 TI-SN74GTLP21395 Datasheet
438Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP22033 TI1-SN74GTLP22033 Datasheet
645Kb / 21P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP22034 TI-SN74GTLP22034 Datasheet
366Kb / 20P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2033 TI-SN74GTLP2033 Datasheet
367Kb / 15P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2034 TI-SN74GTLP2034 Datasheet
435Kb / 21P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
logo
Fairchild Semiconductor
GTLP10B320 FAIRCHILD-GTLP10B320 Datasheet
261Kb / 12P
   10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
GTLP1B151 FAIRCHILD-GTLP1B151 Datasheet
112Kb / 7P
   1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path
logo
Texas Instruments
SN74GTLP1394 TI-SN74GTLP1394 Datasheet
143Kb / 9P
[Old version datasheet]   2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


Datenblatt Download

Go To PDF Page


Link URL




Privatsphäre und Datenschutz
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com