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TL16C2752IFNR Datenblatt(PDF) 10 Page - Texas Instruments |
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TL16C2752IFNR Datenblatt(HTML) 10 Page - Texas Instruments |
10 / 26 page ELECTRICAL CHARACTERISTICS TIMING REQUIREMENTS TL16C2752 SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com 5 V Nominal over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VOH High-level output voltage(2) IOH = –4 mA 4 V VOL Low-level output voltage(2) IOL = 4 mA 0.4 V VCC = 5.5 V, VSS = 0, VI = 0 to 5.5 V, II Input current 10 =A All other terminals floating High-impedance-state VCC = 3.6 V, VSS = 0, VI = 0 to 3.6 V, IOZ =20 =A output current Chip selected in write mode or chip deselected VCC = 5.5 V, TA = 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB, CTSA, CTSB, RIA, and RIB at 2 V, ICC Supply current mA All other inputs at 0.8 V, XTAL1 at 32 MHz, No load on outputs Ci(CLK) Clock input impedance 15 20 pF VCC = 0, VSS = 0, f = 1 MHz, CO(CLK) Clock output impedance 20 30 pF TA = 25°C, All other terminals grounded CI Input impedance 6 10 pF CO Output impedance 10 20 pF (1) All typical values are at VCC = 3.3 V and TA = 25°C. (2) These parameters apply for all outputs except XTAL2. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LIMITS ALT. TEST PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX tw8 Pulse duration, RESET tRESET 1 1 1 1 =s tw1 Pulse duration, clock high tXH 6 25 16 12 8 ns tw2 Pulse duration, clock low tXL tcR Cycle time, read (tw7 + td8 + th7) RC 8 115 80 62 57 ns tcW Cycle time, write (tw6 + td5 + th4) WC 7 115 80 62 57 ns tw6 Pulse duration, IOW or CS tIOW 7 80 55 45 40 ns tw7 Pulse duration, IOR or CS tIOR 8 80 55 45 40 ns Setup time, data valid before IOW ↑ tSU3 tDS 7 25 20 15 15 ns or CS ↑ Hold time, address valid after IOW ↑ th4 tWA 7 20 15 10 10 ns or CS ↑ Hold time, data valid after IOW ↑ or th5 tDH 7 15 10 5 5 ns CS ↑ Hold time, data valid after IOR ↑ or th7 tRA 8 20 15 10 10 ns CS ↑ Delay time, address valid before td5 tAW 7 15 10 7 7 ns IOW ↓ or CS↓ Delay time, address valid to IOR ↓ or td8 tAR 8 15 10 7 7 ns CS ↓ Delay time, IOR ↓ or CS↓ to data td10 tRVD 8 CL = 30 pF 55 35 25 20 ns valid Delay time, IOR ↑ or CS↑ to floating td11 tHZ 8 CL = 30 pF 40 30 20 20 ns data td12 Write cycle to write cycle delay 7 100 75 60 50 ns td13 Read cycle to read cycle delay 8 100 75 60 50 ns 10 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TL16C2752 |
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