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TL16PC564BLVIPZ Datenblatt(PDF) 8 Page - Texas Instruments

Teilenummer TL16PC564BLVIPZ
Bauteilbeschribung  PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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TL16PC564BLVIPZ Datenblatt(HTML) 8 Page - Texas Instruments

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TL16PC564BLVI
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS627− SEPTEMBER 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
subsystem memory map
The subsystem attribute memory space is mapped as follows:
Subsystem Address Bits 8 −0
Attribute Memory Space
0 − 255
CIS
256
CCR0
257
CCR1
258
CCR2
259
CCR3
260
CCR4
261
CCR5
262
CCR6
263
CCR7
The subsystem control space is mapped as follows:
Subsystem Address Bits 8 −0
Control Space
272
Control Register
288
PGMCLK Register (write only)
The subsystem UART space is mapped as follows:
Subsystem Address Bits 8 −0
UART Space
304
UART MCR bit 5 (write only)
304
UART DLL (read only)
305
UART IER (read only)
306
UART FCR (read only)
307
UART LCR (read only)
308
UART MCR (read only)
309
UART LSR (read only)
310
UART MSR (read only)
311
UART DLM (read only)
320
UART transmitter FIFO (read only)
320
UART receiver FIFO (write only)
† Only when serial bypass mode is enabled
host CPU/attribute-memory interface
The host CPU/attribute-memory interface is comprised of one port of the internal DPRAM, the eight CCRs, and
necessary control circuitry. Signals HA0 and CE1 are gated together internally so that the output of the gate is
low when both signals have been asserted by the host CPU. This output is combined with REG and the decoded
address, HA(9−1), to provide the chip enable for the DPRAM and CCRs. This composite chip enable in
combination with WE or OE allows writes and reads to the DPRAM and CCRs.
subsystem/attribute-memory interface
The subsystem/attribute-memory interface is comprised of the second port of the internal DPRAM, the eight
CCRs, and necessary control circuitry. When in multiplexed mode (SSAB = 0), the combination of signals
SELZ /I and ALE(AS) allows either a positive-pulse Intel or a negative-pulse Zilog address latch-enable strobe
to latch the address on SA8 and SAD(7−0). When in the Zilog mode (SELZ/I high), the combination of read/write
[WR(R/W)], data strobe [RD(DS)], and decoded address allows ZBUS access. When in the Intel configuration
(SELZ /I low), the combination of read [RD(DS)], write [WR(R/W)], and decoded address allows IBUS access.
When in nonmultiplexed mode (SSAB = 1), SA(7−0) become the lower-order address bits, SAD(7−0) are strictly
the bidirectional data bus, and ALE(AS) is nonfunctional. All other interface signals function the same.
Not Recommended For New Designs


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