Datenblatt-Suchmaschine für elektronische Bauteile |
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TPD4E001 Datenblatt(PDF) 10 Page - Texas Instruments |
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TPD4E001 Datenblatt(HTML) 10 Page - Texas Instruments |
10 / 28 page 10 TPD4E001 SLLS682L – JULY 2006 – REVISED MAY 2016 www.ti.com Product Folder Links: TPD4E001 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 3. Ensure that there is enough metallization for the VCC and GND loop. During normal operation, the TPD4E001 consumes nA leakage current. But during the ESD event, VCC and GND may see 15 A to 30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike. 4. Leave the unused IO pins floating. In this example of protecting two USB ports, none of the IO pins will be left unused. 5. The VCC pin can be connected in two different ways: (a) If the VCC pin is connected to the system power supply, the TPD4E001 works as a transient suppressor for any signal swing above VCC + VF. A 0.1-μF capacitor on the device VCC pin is recommended for ESD bypass. (b) If the VCC pin is not connected to the system power supply, the TPD4E001 can tolerate higher signal swing in the range up to 10 V. Please note that a 0.1- μF capacitor is still recommended at the VCC pin for ESD bypass. 8.2.3 Application Curve Figure 5 is a capture of the voltage clamping waveform of TPD4E001DRL on IO3 during a +8kV Contact IEC61000-4-2 ESD strike. Figure 5. TPD4E001DRL IEC61000-4-2 Voltage Clamp Waveform +8kV Contact |
Ähnliche Teilenummer - TPD4E001_16 |
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Ähnliche Beschreibung - TPD4E001_16 |
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