Datenblatt-Suchmaschine für elektronische Bauteile |
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TPL5111 Datenblatt(PDF) 8 Page - Texas Instruments |
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TPL5111 Datenblatt(HTML) 8 Page - Texas Instruments |
8 / 25 page LOW FREQUENCY OSCILLATOR FREQUENCY DIVIDER EN/ ONE_SHOT DRVn VDD GND DELAY/ M_DRV DECODER & MANUAL RESET DETECTOR LOGIC CONTROL DONE TPL5111 SNAS659A – JUNE 2015 – REVISED JULY 2015 www.ti.com 7 Detailed Description 7.1 Overview The TPL5111 is a timer with power gating feature. It is ideal for use in power-cycled applications and provides selectable timing from 100 ms to 7200 s. When configured in timer mode (EN/ONE_SHOT= HIGH) the TPL5111 periodically asserts a DRVn signal to an LDO or DC-DC converter that is used to turn on a microcontroller. If the microcontroller replies with a DONE signal within the programmed time interval (< tDRVn) the TPL5111 de-asserts DRVn. Otherwise the TPL5111 asserts DRVn for a time equal to tDRVn. The TPL5111 can also work in a one shot mode (EN/ONE_SHOT= LOW). In this mode the DRVn signal is asserted just one time at the power on of the TPL5111. If the µC replies with a DONE signal within the programmed time interval (< tDRVn) the TPL5111 de-asserts DRVn. Otherwise the TPL5111 asserts DRVn for a time equal to tDRVn. 7.2 Functional Block Diagram 7.3 Feature Description The TPL5111 implements a periodic power gating feature or one shot power gating according to the EN/ONE_SHOT voltage. A manual Power ON function is realized by momentarily pulling the DELAY/M_DRV pin to VDD. 7.3.1 DRVn The DRVn pin may be connected to the enable input of an LDO or DC-DC converter. The pulse generated at DRVn is equal to the programmed time interval period (tIP), minus 50 ms. It is shorter if a DONE signal is received from the µC before tIP - 50 ms. If the DONE signal is not received within tIP - 50 ms, the DRVn signal will be LOW for the last 50 ms of tIP before the next cycle starts. The default value (after resistance reading) is HIGH. The signal is sent out from the TPL5111 when the programmed time interval starts. When the DRVn is HIGH, the manual power ON signal is ignored. 7.3.2 DONE The DONE pin is driven by a µC to signal that the µC is working properly. The TPL5111 recognizes a valid DONE signal as a low to high transition; if two or more DONE signals are received within the time interval, only the first DONE signal is processed. The minimum DONE signal pulse length is 100 ns. When the TPL5111 receives the DONE signal it asserts DRVn logic LOW. 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPL5111 |
Ähnliche Teilenummer - TPL5111_16 |
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