2

INDUSTRIAL TEMPERATURE RANGE

NW6006 ENHANCED TYPE II CALLER ID DECODER

WITH STUTTER DIAL TONE DETECTOR

PIN INFORMATION

Figure 2. Pin Assignment

VREF

IN1+

IN1-

GS1

GND

OSCIN

OSCOUT

CB0

DCLK

DATA

IN2+

IN2-

GS2

CB2

CB1

VCC

CD/STRDT

ST/GT

EST

DR/STD

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

Name

Type

Pin No.

Description

VREF

O

1

Reference Voltage.

This output is used to bias the input OP amp. It is typically VCC/2.

IN1+

I

2

Non-inverting Input of the gain adjustable Tip/Ring OP amp.

IN1-

I

3

Inverting Input of the gain adjustable Tip/Ring OP amp.

GS1

O

4

Gain Select Output of the gain adjustable Tip/Ring OP amp.

The Tip/Ring signal can be attenuated or amplified at GS1 by adjusting the feedback resistor between GS1 and IN1-.

The FSK signal is always detected by Tip/Ring OP amp while DT-AS(CAS) signal can be detected by either Tip/Ring

or Hybrid OP amp. The OP amp selection is controlled by CB1 and CB2 bits.

GND

-

5

Ground.

OSCIN

I

6

Oscillator Input.

A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCOUT. It can also

be driven by an external clock source.

OSCOUT

O

7

Oscillator Output.

A 3.579545 MHz crystal or ceramic resonator should be connected between this pin and the OSCIN. When an

external clock drives OSCIN, this pin can be left floating.

CB0

I

8

Control Bit 0 (FSK Data Interface Mode Select).

This pin can select the 3-wire FSK data interface mode. A ‘0’ on this pin indicates interface mode 0; while a ‘1’ on

this pin indicates interface mode 1. (The FSK data interface is consisted of DATA, DCLK and DR/STD pins.)

When CB0 is high and CB1, CB2 are both low, the device is set into the power down state.

DCLK

I/NC

9

Data Clock of the Serial FSK Interface.

In mode 0 (CB0 is low), this pin is unused; In mode 1 (CB0 is high), this pin is an input which clock the FSK data

byte out to the DATA pin.

DATA

O

10

Data Output of the Serial FSK Interface.

In mode 0 (CB0 is low), the FSK serial bit stream is output to the DATA pin directly.

In mode 1 (CB0 is high), the start bit is stripped off, the data byte and the stop bit is stored in a 9-bit buffer. At the

end of each word signaled by the DR/STD pin, the microcontroller should shift the byte out onto the DATA pin by