Datenblatt-Suchmaschine für elektronische Bauteile |
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AD15700 Datenblatt(PDF) 7 Page - Analog Devices |
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AD15700 Datenblatt(HTML) 7 Page - Analog Devices |
7 / 44 page REV. A AD15700 –7– 14-BIT DAC TIMING CHARACTERISTICS1, 2 (VDD = 5 V, 5%, VREF = 2.5 V, AGND = DGND = 0 V. All Specifications TA = TMIN to TMAX, unless otherwise noted). Parameter Limit at TMIN, TMAX All Versions Unit Description fSCLK 25 MHz max SCLK Cycle Frequency t1 40 ns min SCLK Cycle Time t2 20 ns min SCLK High Time t3 20 ns min SCLK Low Time t4 15 ns min CS_DAC Low to SCLK High Setup t5 15 ns min CS_DAC High to SCLK High Setup t6 35 ns min SCLK High to CS_DAC Low Hold Time t7 20 ns min SCLK High to CS_DAC High Hold Time t8 15 ns min Data Setup Time t9 0 ns min Data Hold Time t10 30 ns min CS_DAC High Time between Active Periods NOTES 1Guaranteed by design. Not production tested. 2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of 3 V and timed from a voltage level of 1.6 V). Specifications subject to change without notice. t 2 t 3 t 7 t 5 t 8 t 9 t 1 t 6 t 4 t 10 DB13 DB0 DIN CS_DAC SCLK Figure 3. Timing Diagram |
Ähnliche Teilenummer - AD15700 |
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Ähnliche Beschreibung - AD15700 |
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