WAKE

VDD

DONE

RSTn

DELAY/

M_RST

6

TPL5010-Q1

SNAS679 – SEPTEMBER 2016

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(1)

Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through

correlations using statistical quality control (SQC) method.

(2)

Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(3)

This parameter is specified by design and/or characterization and is not tested in production.

(4)

In case of RSTn from its falling edge, in case of WAKE, from its rising edge.

7.6 Timing Requirements

UNIT

Capacitive load 50 pF, Rpull-up 100 kΩ

11

µs

Capacitive load 50 pF, Rpull-up 100 kΩ

50

ns

Capacitive load 50 pF

50

ns

Capacitive load 50 pF

50

ns

DONE to RSTn or WAKE to

DONE delay

100

ns

ms

Observation time 30 ms

20

ms

De-bounce manual reset

20

ms

Figure 1. TPL5010-Q1 Timing