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SLB9665TT2.0 Datenblatt(PDF) 10 Page - Infineon Technologies AG |
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SLB9665TT2.0 Datenblatt(HTML) 10 Page - Infineon Technologies AG |
10 / 24 page Data Sheet 10 Revision 1.0 2015-10-27 SLB 9665 TPM2.0 Trusted Platform Module Pin Description Figure 4-2 Pinout of the SLB 9665VQ2.0 / SLB 9665XQ2.0 (PG-VQFN-32-13 Package, Top View) Table 4-1 Buffer Types Buffer Type Description TS Tri-State pin ST Schmitt-Trigger pin OD Open-Drain pin Table 4-2 I/O Signals Pin Number Name Pin Type Buffer Type Function PG-TSSOP- 28-2 PG-VQFN- 32-13 26 27 LAD0 I/O TS LPC Address/Data Bit 0 Multiplexed LPC command, address and data bus. Connect these pins to the LAD[3:0] pins of the LPC host. 23 24 LAD1 I/O TS LPC Address/Data Bit 1 see description of LAD0 above. 20 21 LAD2 I/O TS LPC Address/Data Bit 2 see description of LAD0 above. 17 19 LAD3 I/O TS LPC Address/Data Bit 3 see description of LAD0 above. 22 23 LFRAME# I ST LPC Framing Signal LPC framing signal. This pin is connected to the LPC LFRAME# signal and indicates the start of a new cycle on the LPC bus or the termination of a broken cycle. The signal is active low. LAD1 TPM SLB 9665 VQ 2.0 PG-VQFN-32-13 1 10 15 26 30 18 LFRAME# LCLK LAD2 VDD LAD3 LRESET# NC 22 7 VDD GPIO NC NC NC NC NC NC |
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Ähnliche Beschreibung - SLB9665TT2.0 |
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