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TSB83AA22C Datenblatt(PDF) 10 Page - Texas Instruments

Teilenummer TSB83AA22C
Bauteilbeschribung  PHY and OHCI Link Device
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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TSB83AA22C Datenblatt(HTML) 10 Page - Texas Instruments

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Description
TSB83AA22C IEEE Std 1394b-2002
PHY and OHCI Link Device
SLLS802 – FEBRUARY 2007
Initial-Channels-Available Registers
• Digital Video and Audio Performance
Enhancements
The TSB83AA22C is an IEEE Std 1394b-2002 link-layer design and physical layer (PHY) design
combined in a single package to meet the demanding requirements of today’s 1394 bus applications. The
TSB83AA22C device is capable of exceptional 800-Mbps performance; thus, providing the throughput and
bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB83AA22C
device also provides outstanding ultralow power operation and intelligent power-management capabilities.
The device provides the IEEE 1394 LLC function and PHY function and is compatible with 100-Mbps,
200-Mbps, 400-Mbps, and 800-Mbps serial-bus data rates.
The TSB83AA22C operates as the interface between 33-MHz/32-bit PCI local bus and an IEEE Std
1394a-2000 or IEEE Std 1394b-2002 serial-bus interface. It is capable of supporting serial data rates at
98.304, 196.608, 393.216, 491.52, or 786.432 Mbps (referred to as S100, S200, S400, S400B, or S800
speeds, respectively). When acting as a PCI bus master, the TSB83AA22C device is capable of multiple
cache-line bursts of data, which can transfer at 132M bytes/s for 32-bit transfers after connecting to the
memory controller.
Due to the high throughput potential of the TSB83AA22C device, it possible to encounter large PCI and
legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential
problem, the TSB83AA22C implements deep transmit and receive FIFOs (see Section 1.1, Features, for
FIFO size information) to buffer the 1394 data, thus, preventing possible problems due to bus latency.
This also ensures that the device can transmit and receive sustained maximum-size isochronous or
asynchronous data payloads at S800.
The TSB83AA22C LLC section implements other performance enhancements to improve overall
performance of the device, such as a highly-tuned physical data path for enhanced SBP-2 performance,
physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration.
The TSB83AA22C LLC section also implements hardware enhancements to better support digital video
(DV) and MPEG data stream reception and transmission. These enhancements are enabled through the
isochronous receive digital video enhancements register at TI extension offset A80h (see Section 6.3.4,
Isochronous Receive Digital Video Enhancements Register). These enhancements include automatic
time-stamp insertion for transmitted DV and MPEG-formatted streams, and common isochronous packet
(CIP) header stripping for received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous
data contexts are implemented as hardware support for the synchronization time stamp for both DV and
audio/video CIP formats. The TSB83AA22C device supports modification of the synchronization
time-stamp field to ensure that the value inserted via software is not stale — that is, less than the current
cycle timer when the packet is transmitted.
The TSB83AA22C performance and enhanced throughput make it an excellent choice for today’s 1394
PC market; however, portable, mobile, and even desktop PC power-management schemes continue to
require devices to use less and less power, and TI’s 1394 product line has continued to raise the bar by
providing the lowest-power 1394 devices in the industry. The TSB83AA22C device represents the next
evolution of TI commitment to meet the challenge of power-sensitive applications. The TSB83AA22C
device has ultralow operational power requirements and intelligent power-management capabilities that
allow it to conserve power autonomously based on the device usage. The TSB83AA22C LLC section fully
supports D0, D1, D2, and D3hot/cold power states, as specified in the PC 2001 Design Guide requirements
and the PCI Power Management Specification. PME wake-event support is subject to operating-system
support and implementation.
Introduction
10
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