MC100LVEL33

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2

Figure 1. Logic Diagram and Pinout Assignment

4

3

1

2

5

6

7

8

Q

Q

CLK

R

÷4

Reset

CLK

CLK*, CLK**

ECL Differential Clock Inputs

Q, Q

ECL Differential Data ÷4 Outputs

Reset*

ECL Asynch Reset

Reference Voltage Output

Positive Supply

Negative Supply

Table 1. PIN DESCRIPTION

* Pins will default LOW when open due to internal 75 kW

PIN

FUNCTION

Table 2. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

PECL Mode Power Supply

8 to 0

V

NECL Mode Power Supply

−8 to 0

V

PECL Mode Input Voltage

NECL Mode Input Voltage

6 to 0

−6 to 0

V

Output Current

Continuous

Surge

50

100

mA

± 0.5

mA

Operating Temperature Range

−40 to +85

°C

Storage Temperature Range

−65 to +150

°C

Thermal Resistance (Junction-to-Ambient)

0 lfpm

500 lfpm

SOIC−8 NB

SOIC−8 NB

190

130

°C/W

Thermal Resistance (Junction-to-Case)

Standard Board

SOIC−8 NB

41 to 44 ±5%

°C/W

Thermal Resistance (Junction-to-Ambient)

0 lfpm

500 lfpm

TSSOP−8

TSSOP−8

185

140

°C/W

Thermal Resistance (Junction-to-Case)

Standard Board

TSSOP−8

41 to 44 ±5%

°C/W

Wave Solder (Pb-Free)

< 2 to 3 sec @ 260°C

265

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.