Datenblatt-Suchmaschine für elektronische Bauteile |
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BU2362FV Datenblatt(PDF) 4 Page - Rohm |
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BU2362FV Datenblatt(HTML) 4 Page - Rohm |
4 / 23 page BU2362FV 4/19 TSZ02201-0E3E0J500680-1-2 © 2015 ROHM Co., Ltd. All rights reserved. 04.Nov.2015 Rev.001 www.rohm.com TSZ22111・15・001 Absolute Maximum Ratings (Ta=25°C) Parameter Symbol Rating Unit Supply Voltage VDD -0.5 to +7.0 V Input Voltage VIN -0.5 to VDD+0.5 V Storage Temperature Range Tstg -30 to +125 °C Power Dissipation Pd 0.45 (Note 1) W (Note 1) In the case of exceeding Ta = 25°C, 4.5mW to be reduced per 1°C (Note) Operating is not guaranteed. (Note) Power dissipation is measured when the IC is mounted to the printed circuit board. Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Recommended Operating Conditions Parameter Symbol Limit Unit Supply Voltage VDD 2.7 to 3.6 V Input “H” Voltage VIH 0.8VDD to VDD V Input “L” Voltage VIL 0.0 to 0.2VDD V Operating Temperature Topr -25 to +85 °C Output Load CL 15 pF Electrical Characteristics (VDD=3.3V, Ta=25°C, Crystal frequency 27.0000MHz, unless otherwise specified.) Parameter Symbol Limit Unit Conditions Min Typ Max Output L Voltage VOH 2.4 - - V IOH=-4.0mA Output H Voltage VOL - - 0.4 V IOL=4.0mA Action Circuit Current IDD - 35 45 mA At no load CLK512FS CLK512-44 - 22.5792 - MHz At FSEL1=OPEN XTAL x 3136/625/6 CLK512-48 - 24.5760 - MHz At FSEL1=L XTAL x 2048/375/6 CLKA CLKA-A - 16.9344 - MHz At FSEL1=OPEN XTAL x 3136/625/8 CLKA-B - 36.8640 - MHz At FSEL1=L XTAL x 2048/375/8 CLK36M CLK36M - 36.8640 - MHz XTAL x 2048/375/4 CLK33M CLK33M - 33.8688 - MHz XTAL x 3136/625/4 CLK16M CLK16M - 16.9344 - MHz XTAL x 3136/625/8 CLK27M CLK27M - 27.0000 - MHz XTAL direct out Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD Period-Jitter 1 σ P-J 1 σ - 70 - psec (Note 1) Period-Jitter MIN-MAX P-J MIN-MAX - 420 - psec (Note 2) Rise Time tR - 2.5 - nsec Period of transition time required for The output reach 80% from 20% of VDD. Fall Time tF - 2.5 - nsec Period of transition time required for The output reach 20% from 80% of VDD. Output Lock-Time tLOCK - - 1 msec (Note 3) (Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN. If the input frequency is set to 27.0000MHz, the output frequency will be as listed above. (Note 1) Period-Jitter 1 σ This parameter represents standard deviation ( 1 ) on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. (Note 2) Period-Jitter MIN-MAX This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd. (Note 3) Output Lock-Time The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is switched from Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency, respectively. |
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