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CS8412 Datenblatt(PDF) 8 Page - Cirrus Logic |
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CS8412 Datenblatt(HTML) 8 Page - Cirrus Logic |
8 / 38 page CS8411 CS8412 8 DS61F1 CS8411 DESCRIPTION The CS8411 is more flexible than the CS8412 but requires a microcontroller or DSP to load internal registers. The CS8412 does not have internal regis- ters so it may be used in a stand-alone mode where no microprocessor or DSP is available. The CS8411 accepts data from a transmission line coded according to the digital audio interface stan- dards. The I.C. recovers clock and data, and sepa- rates the audio data from control information. The audio data is output through a configurable serial port and the control information is stored in internal dual-port RAM. Extensive error reporting is avail- able via internal registers with the option of repeat- ing the last sample when an error occurs. A block diagram of the CS8411 is shown in Figure 4. Parallel Port The parallel port accesses two status registers, two interrupt enable registers, two control registers, and 28 bytes of dual-port buffer memory. The status registers and interrupt enable registers occupy the same address space. A bit in control register 1 se- lects the two registers, either status or interrupt en- able, that occupy addresses 0 and 1 in the memory map. The address bus and the RD/WR line should be valid when CS goes low. If RD/WR is low, the value on the data bus will be written into the buffer memory at the specified address. If RD/WR is high, the value in the buffer memory, at the specified ad- dress, is placed on the data bus. Detailed timing for the parallel port can be found in the Switching Characteristics - Parallel Port table. The memory space on the CS8411 is allocated as shown in Figure 5. There are three defined buffer modes selectable by two bits in control register 1. Further information on the buffer modes can be found in the Control Registers section. Status and IEnable Registers The status and interrupt enable registers occupy the same address space. The IER/SR bit in control reg- ister 1 selects whether the status registers (IER/SR = 0) or the IEnable registers (IER/SR = 1) occupy addresses 0 and 1. Upon power-up, the control and IEnable registers contain all zeros; therefore, the 10 2 10 3 10 4 10 5 10 6 5 0 - 5 - 10 - 15 - 20 - 25 - 30 Jitter Frequency (Hz) Figure 3. Jitter Attenuator Characteristics |
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Ähnliche Beschreibung - CS8412 |
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