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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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DM9102AT Datenblatt(PDF) 8 Page - List of Unclassifed Manufacturers |
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DM9102AT Datenblatt(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 77 page  DM9102A Single Chip Fast Ethernet NIC controller 8 Final Version: DM9102A-DS-F03 August 28, 2000 destination address of the data transfer is recognized by a target. 27 STOP# I/O Stop This signal is asserted low by the target device to request the master device to stop the current transaction. 30 PERR# I/O Parity Error The DM9102A as a master or slave will assert this signal low to indicate a parity error on any incoming data. 31 SERR# I/O System Error This signal is asserted low when address parity is detected with PCICS bit31 (detected parity error) Is enabled. The system error asserts two clock cycles after the falling address if an address parity error is detected. 33 PAR I/O Parity This signal indicates even parity across AD0~AD31 and C/BE0#~C/BE3# including the PAR pin. This signal is an output for the master and input for the slave device. It is stable and valid one clock after the address phase. 2 20 34 48 C/BE3# C/BE2# C/BE1# C/BE0# I/O Bus Command/Byte Enable During the address phase, these signals define the bus command or the type of bus transaction that will take place. During the data phase these pins indicate which byte lanes contain valid data. C/BE0# applies to bit7-0 and C/BE3# applies to bit31-24. 121,122,123,124,126,127, 128,1,6,7,10, 11,13,14,16, 17,38,39,40, 41,43,44,47, 49,50,51,54, 55,56,57,59, 60 AD31~AD0 I/O Address & Data These are multiplexed address and data bus signals. As a bus master, the DM9102A will drive address during the first bus phase. During subsequent phases, the DM9102A will either read or write data expecting the target to increment its address pointer. As a target, the DM9102A will decode each address on the bus and respond if it is the target being addressed. Boot ROM and EEPROM Interface (Including multiplex mode or direct mode) Multiplex mode Pin No. 128QFP/128TQFP Pin Name I/O Description 62,63,64,65, 66,67,68,69 BPAD0~BPAD7 (BPAD7/LEDMODE) I/O, LI Boot ROM address and data bus (bits 0~7) Boot ROM address and data multiplexed lines bits 0~7. In MUX mode, there are two consecutive address cycles, these lines contain the boot ROM address pins 7~2, out_enable and write_enable of Boot ROM in the first cycle; and these lines contain address pins 15~8 in second cycle. After the first two cycles, these lines contain data bit 7~0 in consective cycles. BPAD1 is also a reset latch pin. It is Boot ROM address and data bus when normal operation. When at power on reset, it is used to pull up or down externally through a resister to select |
Ähnliche Teilenummer - DM9102AT |
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Ähnliche Beschreibung - DM9102AT |
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