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CAT25128XE-T2 Datenblatt(PDF) 7 Page - ON Semiconductor |
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CAT25128XE-T2 Datenblatt(HTML) 7 Page - ON Semiconductor |
7 / 20 page CAT25128 http://onsemi.com 7 Status Register The Status Register, as shown in Table 11, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non−volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 12. The protected blocks then become read−only. The WPEN (Write Protect Enable) bit acts as an enable for the WP pin. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1. This condition prevents writing to the status register and to the block protected sections of memory. While hardware write protection is active, only the non−block protected memory can be written. Hardware write protection is disabled when the WP pin is high or the WPEN bit is 0. The WPEN bit, WP pin and WEL bit combine to either permit or inhibit Write operations, as detailed in Table 13. The IPL (Identification Page Latch) bit determines whether the additional Identification Page (IPL = 1) or main memory array (IPL = 0) can be accessed both for Read and Write operations. The IPL bit is set by the user with the WRSR command and is volatile. The IPL bit is automatically reset after read/write operations. The LIP bit is set by the user with the WRSR command and is non−volatile. When set to 1, the Identification Page is permanently write protected (locked in Read−only mode). Note: The IPL and LIP bits cannot be set to 1 using the same WRSR instruction. If the user attempts to set (“1”) both the IPL and LIP bit in the same time, these bits cannot be written and therefore they will remain unchanged. Table 11. STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN IPL* 0 LIP* BP1 BP0 WEL RDY *The IPL and LIP bits are available for the New Product only. The Status Register bit 6 and bit 4 are set to “0” for the older product revisions. Table 12. BLOCK PROTECTION BITS Status Register Bits Array Address Protected Protection BP1 BP0 0 0 None No Protection 0 1 3000−3FFF Quarter Array Protection 1 0 2000−3FFF Half Array Protection 1 1 0000−3FFF Full Array Protection Table 13. WRITE PROTECT CONDITIONS WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable |
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Ähnliche Beschreibung - CAT25128XE-T2 |
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