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LM2647MTC Datenblatt(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teilenummer LM2647MTC
Bauteilbeschribung  Dual Synchronous Buck Regulator Controller
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Hersteller  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM2647MTC Datenblatt(HTML) 4 Page - National Semiconductor (TI)

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Pin Description (Continued)
permitted. If not, the upper FET will be turned OFF and will
stay so for several cycles if necessary, until the current
returns to normal. Eventually, if the overcurrent condition
persists, and the upper FET has not been turned ON, the
output will clearly start to fall. Ultimately the output will fall
below the under-voltage threshold, and a fault condition will
be asserted by the IC.
Pin 16, SW2: The Switching node of the buck regulator of
Channel 2. Also serves as the lower rail of the floating driver
of the upper FET.
Pin 17, HDRV2: Gate drive pin for the upper FET of Channel
2 (High-side drive). The top gate driver is interlocked with the
bottom
gate
driver
to
prevent
shoot-through/cross-
conduction.
Pin 18, BOOT2: Bootstrap pin for Channel 2. This is the
upper supply rail for the floating driver of the upper FET. It is
bootstrapped by means of a ceramic capacitor connected to
the channel Switching node. This capacitor is charged up by
the IC to a value of about 5V as derived from the V5 pin (Pin
21).
Pin 19, PGND2: Power Ground pin of Channel 2. This is the
return path for the bottom FET gate drive. Both the PGND’s
are to be connected on the PCB to the system ground and
also to the Signal ground (Pin 7) in accordance with the
recommended Layout Guidelines .
Pin 20, LDRV2: Gate drive pin for the Channel 2 bottom FET
(Low-side drive). The bottom gate driver is interlocked with
the
top
gate
driver
to
prevent
shoot-through/cross-
conduction. It is always latched high when a fault condition is
asserted by the IC.
Pin 21, V5: Upper rail of the lower FET drivers of both
channels. Also used to charge up the bootstrap capacitors of
the upper FET drivers. This is connected to an external 5V
supply. The 5V rail may be the same as the rail used to
provide power to the VDD pin (Pin 5), but the VDD pin will
then require to be well-decoupled so that it does not interact
with the V5 pin. A low-pass RC filter consisting of a ceramic
0.1µF capacitor (preferably 0.22µF) and a 10
Ω resistor will
suffice as shown in the Typical Applications circuit.
Pin 22, VIN: The input to both the Buck regulator power
stages. It also is used by the internal ramp generator to
implement the line feedforward feature. The VIN pin is also
used with the SENSE pin voltage to predict the CCM (con-
tinuous conduction mode) duty cycle and to thereby set the
minimum allowed DCM duty cycle to 85% of the CCM value
(in SKIP mode, see Pin 10). This is a high input impedance
pin, drawing only about 100µA (typical) from the input rail.
Pin 23, LDRV1: LDRV pin of Channel 1. See Pin 20.
Pin 24, PGND1: PGND pin for Channel 1.See Pin 19.
Pin 25, BOOT1: Boot pin of Channel 1. See Pin 18.
Pin 26, HDRV1: HDRV pin of Channel 1. See Pin 17.
Pin 27, SW1: SW pin of Channel 1. See Pin 16.
Pin 28, ILIM1: Channel 2 Current Limit pin. See Pin 15.
www.national.com
4


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