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BD37531FV Datenblatt(PDF) 11 Page - Rohm

Teilenummer BD37531FV
Bauteilbeschribung  Sound Processor with Built-in 3-band Equalizer
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Hersteller  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD37531FV Datenblatt(HTML) 11 Page - Rohm

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BD37531FV
11/30
TSZ02201-0C2C0E100520-1-2
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
16.Dec.2015 Rev.001
Timing Chart
CONTROL SIGNAL SPECIFICATION
(1) Electrical Specifications and Timing for Bus Lines and I/O Stages
Figure 21. Definition of Timing on the I2C-bus
Table 1 Characteristics of the SDA and SCL bus lines for I2C-bus devices
(Unless specified particularly, Ta=25°C, VCC=8.5V)
Parameter
Symbol
Fast-mode I2C-bus
Unit
Min
Max
1
SCL clock frequency
fSCL
0
400
kHz
2
Bus free time between a STOP and START condition
tBUF
1.3
μS
3
Hold time (repeated) START condition. After this period, the first clock
pulse is generated
tHD;STA
0.6
μS
4
LOW period of the SCL clock
tLOW
1.3
μS
5
HIGH period of the SCL clock
tHIGH
0.6
μS
6
Set-up time for a repeated START condition
tSU;STA
0.6
μS
7
Data hold time:
tHD;DAT
0.06 (Note)
μS
8
Data set-up time
tSU;DAT
120
ns
9
Set-up time for STOP condition
tSU;STO
0.6
μS
All values referred to VIH
Min and VIL Max Levels (see Table 2).
(Note) The device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH Min of the SCL signal) in order to bridge the
undefined region of the falling edge of SCL.
About 7(tHD;DAT), 8(tSU;DAT), make the setup in which the margin is fully in .
Table 2 Characteristics of the SDA and SCL I/O stages for I2C-bus devices
Parameter
Symbol
Fast-mode devices
Unit
Min
Max
10
LOW level input voltage:
VIL
-0.3
+1
V
11
HIGH level input voltage:
VIH
2.3
5
V
12
Pulse width of spikes which must be suppressed by the input filter.
tSP
0
50
ns
13
LOW level output voltage: at 3mA sink current
VOL1
0
0.4
V
14
Input current each I/O pin with an input voltage between 0.4V and 4.5V.
II
-10
+10
μA
SDA
S
SCL
tLOW
tR
tHD;DAT
P
tHD;STA
tHIGH
tBUF
t
F
tSU;DAT
tSU;STAT
tSU;STOT
tSP
tHD;STAT
Sr
P
Figure 22. A Command Timing Example in the I2C Data Transmission
tBUF
:4us
tHD;STA
:2us
tHD;DAT
:1us
tLOW
:3us
tHIGH
:1us
tSU;DAT
:1us
tSU;STO
:2us
SCL clock frequency:250kHz
SCL
SDA
tHD;STA
:2µs
tHD;DAT
:1µs
tSU;DAT
:1µs
tSU;STO
:2µs
tBUF
:4µs
tLOW
:3µs
tHIGH
:1µs
SDA
SCL
SCL clock frequency : 250kHz


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