Datenblatt-Suchmaschine für elektronische Bauteile |
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54LS168DMQB Datenblatt(PDF) 4 Page - National Semiconductor (TI) |
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54LS168DMQB Datenblatt(HTML) 4 Page - National Semiconductor (TI) |
4 / 6 page Functional Description The ’LS168 uses edge-triggered D-type flip-flops and has no constraints on changing the control or data input signals in either state of the Clock The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter The parallel load opera- tion takes precedence over the other operations as indicat- ed in the Mode Select Table When PE is LOW the data on the P0 – P3 inputs enters the flip-flops on the next rising edge of the Clock In order for counting to occur both CEP and CET must be LOW and PE must be HIGH The UD input then determines the direction of counting The Termi- nal Count (TC) output is normally HIGH and goes LOW provided that CET is LOW when a counter reaches zero in the COUNT DOWN mode or reaches 9 in the COUNT UP mode The TC output state is not a function of the Count Enable Parallel (CEP) input level The TC output of the ’LS168 decade counter can also be LOW in the illegal states 11 13 and 15 which can occur when power is turned on or via parallel loading If an illegal state occurs the ’LS168 will return to the legitimate sequence within two counts Since the TC signal is derived by decoding the flip- flop states there exists the possibility of decoding spikes on TC For this reason the use of TC as a clock signal is not recommended (see logic equation below) 1 Count Enable e CEP CET PE 2 Up TC e Q0 Q3 (UD) CET 3 Down TC e Q0 Q1 Q2 Q3 (UD) CET ’LS168 Mode Select Table PE CEP CET UD Action on Rising Clock Edge L X X X Load (Pn xQn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial State Diagram TLF10207 – 3 Logic Diagram TLF10207 – 4 4 |
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