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ADS8699IRUMT Datenblatt(Datasheet) 10 Page - TI store

Teile-Nr. ADS8699IRUMT
Beschreibung  18-Bit, High-Speed, Single-Supply, SAR ADC Data Acquisition System with Programmable, Bipolar Input Ranges
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Hersteller  TI1 [TI store]
Homepage  http://www.ti.com
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ADS8691, ADS8695, ADS8699
SBAS777 – DECEMBER 2016
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Product Folder Links: ADS8691 ADS8695 ADS8699
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Copyright © 2016, Texas Instruments Incorporated
6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock)
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
fCLK
Serial clock frequency
66.67
MHz
tCLK
Serial clock time period
1/fCLK
tPH_CK
SCLK high time
0.45
0.55
tCLK
tPL_CK
SCLK low time
0.45
0.55
tCLK
TIMING SPECIFICATIONS
tDEN_CSDO
Delay time: CONVST/CS falling edge to data enable
9.5
ns
tDZ_CSDO
Delay time: CONVST/CS rising to SDO-x going to 3-state
10
ns
tD_CKRVS_r
Delay time: SCLK rising edge to RVS rising
14
ns
tD_CKRVS_f
Delay time: SCLK falling edge to RVS falling
14
ns
tD_RVSDO
Delay time: RVS rising to (next) data valid on SDO-x
2.5
ns
tD_CSRVS
Delay time: CONVST/CS rising edge to RVS displaying internal device state
15
ns
6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX
UNIT
TIMING SPECIFICATIONS
tDEN_CSDO
Delay time: CONVST/CS falling edge to data enable
9.5
ns
tDZ_CSDO
Delay time: CONVST/CS rising to SDO-x going to 3-state
10
ns
tDEN_CSRVS
Delay time: CONVST/CS falling edge to first rising edge on RVS
50
ns
tD_RVSDO
Delay time: RVS rising to (next) data valid on SDO-x
2.5
ns
tINTCLK
Time period: internal clock
15
ns
tCYC_RVS
Time period: RVS signal
15
ns
tWH_RVS
RVS high time
0.4
0.6
tINTCLK
tWL_RVS
RVS low time
0.4
0.6
tINTCLK
tD_CSRVS
Delay time: CONVST/CS rising edge to RVS displaying internal
device state
15
ns




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