Data Sheet

ADF4356

Rev. 0 | Page 5 of 35

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Normalized In-Band Phase Noise Floor

−225

dBc/Hz

−227

dBc/Hz

−121

dBc/Hz

10 kHz offset; normalized to 1 GHz

97

fs

Spurious Signals Due to PFD Frequency

−85

dBc

1

2

3

4

RF output power using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. Unused RF output pins are terminated in 50 Ω.

5

Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

6

Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

7

ADIsimPLL design tool.

8

Integrated RMS jitter using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. The EV-ADF4356SD1Z evaluation board is configured to

accept a single ended REFIN (SMA 100) = 160 MHz, VCO frequency = 6 GHz, PFD frequency = 80 MHz, charge pump current = 0.9 mA, and bleed current is off. The loop

filter is configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated in 50 Ω.

TIMING CHARACTERISTICS

Table 2. Write Timing

Parameter

Limit

Unit

Description

50

MHz max

Serial peripheral interface CLK frequency

10

ns min

LE setup time

5

ns min

DATA to CLK setup time

5

ns min

DATA to CLK hold time

10

ns min

CLK high duration

10

ns min

CLK low duration

10

ns min

CLK to LE setup time

whichever is longer

ns min

LE pulse width

Write Timing Diagram

CLK

DATA

LE

DB31 (MSB)

DB30

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

DB2

(CONTROL BIT C3)

DB3

(CONTROL BIT C4)

Figure 2. Write Timing Diagram