INDUSTRIALTEMPERATURERANGE

2

IDT74ALVCH162373

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SSOP/ TSSOP

TOP VIEW

PIN CONFIGURATION

1

GND

GND

GND

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

40

41

42

43

44

45

46

47

48

1

1

1

OE

1

1

1

1

1

1

2

2

2

2

2

2

GND

2

2

2

OE

1

GND

GND

GND

1

1

LE

1

1

1

1

1

1

2

2

2

2

2

2

GND

2

2

2

LE

NOTE:

1. As applicable to the device type.

Symbol

Conditions

Typ.

Max.

Unit

Input Capacitance

5

7

pF

Output Capacitance

7

9

pF

I/O Port Capacitance

7

9

pF

Symbol

Description

Max

Unit

–0.5 to +4.6

V

V

Storage Temperature

–65 to +150

°C

DC Output Current

–50 to +50

mA

Continuous Clamp Current,

±50

mA

–50

mA

Continuous Current through each

±100

mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

Pin Names

Description

xDx

xLE

LatchEnableInputs

xQx

3-StateOutputs

xOE

3-StateOutputEnableInput(ActiveLOW)

PIN DESCRIPTION

Inputs

Outputs

xOE

xLE

xDx

xQx

LH

H

H

LH

L

L

HX

X

Z

LL

X

Q

o

(2)

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

2. Output level before the indicated steady-state input conditions were established.