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MC145421 Datenblatt(PDF) 5 Page - Motorola, Inc |
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MC145421 Datenblatt(HTML) 5 Page - Motorola, Inc |
5 / 16 page MC145421 •MC145425 MOTOROLA 5 MC145421 MASTER PIN DESCRIPTIONS VDD Positive Supply (Pin 24) The most positive power supply pin, normally + 5 V with respect to VSS. VSS Negative Supply (Pin 1) The most negative supply pin and logic ground, normally 0 V. Vref Reference Output (Analog Ground) (Pin 2) This pin is the output of the internal reference supply and should be bypassed to VDD and VSS with 0.1 µF capacitors. This pin usually serves as an analog ground reference for transformer coupling of the device’s incoming bursts from the line. No external dc load should be placed on this pin. LI Line Input (Pin 3) This pin is an input to the demodulator for the incoming bursts. The input has an internal 240 k Ω resistor tied to the Vref pin, so an external capacitor or line transformer may be used to couple the input signal to the device with no dc offset. LO1, LO2 Line Driver Outputs (Pins 23, 22) These push–pull outputs drive the twisted pair transmis- sion line with a 512 kHz modified DPSK (MDPSK) burst each 125 µs, in other words at an 8 kHz rate. When not modulating the line, these pins are driven to the active high state — being the same potential, they create an ac short. When used in conjunction with feed resistors, proper line termina- tion is maintained. SE Signal Enable Input (Pin 11) At the time of a negative transition on this pin, an internal latch stores the states of LB and PD for as long as SE is held low. During this time, the VD, DO1, and DO2 outputs are driven to the high–impedance state. When SE is high, all pins function normally. LB Loopback Control (Pin 4) A low level on this pin ties the internal modulator output to the internal demodulator input, which loops the entire burst for testing purposes. During the loopback operation, the LI input is ignored and the LO1 and LO2 drivers are driven to the active high level. The state of this pin is internally latched if the SE pin is held low. This feature is only active when the PD input is high. PD Power–Down Input (Pin 12) When held low the ISDN UDLT powers down, except the circuitry that is necessary to demodulate an incoming burst and to output VD, B, and D channel data bits. When PD is brought high, the ISDN UDLT powers up. Then, it begins transmitting every MSI period to the slave device, shortly after the rising edge of MSI. The state of this pin is latched if the SE pin is held low. VD Valid Data Output (Pin 5) A high level on this pin indicates that a valid line transmis- sion has been demodulated. A valid transmission burst is determined by proper synchronization and the absence of detected bit errors. VD changes state on the rising edge of MSI when PD is high. When PD is low, VD changes state at the end of demodulation of a transmission burst and does not change again until three MSI rising edges have occurred, at which time it goes low, or until the next demodulation of a burst. VD is a standard B–series CMOS output and is high impedance when SE is low. MSI Master Sync Input (Pin 16) This pin is the master, 8 kHz frame reference input. The rising edge of MSI loads B and D channel data which had been input during the previous frame into the modulator sec- tion of the device and initiates the outbound burst onto the twisted–pair cable. The rising edge of MSI also initiates the buffering of the B and D channel data demodulated during the previous frame. MSI should be approximately leading edge aligned with the TDC/RDC data clock input pin. CCI High–Speed Clock Input (Pin 17) An 8.192 MHz clock should be supplied to this input. The 8.192 MHz input should be 50% duty cycle. However, it may free–run with respect to all other clocks without performance degradation. D1I, D2I D Channel Signaling Bit Inputs (Pins 6, 7) These inputs are 16 kbps serial data inputs. Two bits should be clocked into each of these inputs between the ris- ing edges of the MSI frame reference clock. The first bit of each D channel is clocked into an intermediate buffer on the first falling edge of the DCLK following the rising edge of MSI. The second bit of each D channel is clocked in on the next negative transition of the DCLK. If further DCLK negative edges occur, new information is serially clocked into the buff- er replacing the previous data one bit at a time. Buffered D channel data bits are burst to the slave device on the next rising edge of the MSI frame reference clock. D1O, D2O D Channel Signal Outputs (Pins 9, 10) These serial outputs provide the 16 kbps D channel signal- ing information from the incoming burst. Two data bits should be clocked out of each of these outputs between the rising edges of the MSI frame reference clock. The rising edge of MSI produces the first bit of each D channel on its respective pin. Circuitry then searches for a negative D channel clock edge. This tells the D channel data shift register to produce the second D channel bit on the next rising edge of the DCLK. Further positive edges of the DCLK recirculate the D channel output buffer information. |
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