SL28PCIe16

DOC#: SP-AP-0790 (Rev. 0.3)

Page 3 of 12

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in Table 1.

The block write and block read protocol is outlined in Table 2

while Table 3 outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h).

Control Registers

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

1Start

1

Start

8:2

Slave address–7 bits

8:2

Slave address–7 bits

9

Write

9

Write

10

Acknowledge from slave

10

Acknowledge from slave

18:11

Command Code–8 bits

18:11

Command Code–8 bits

19

Acknowledge from slave

19

Acknowledge from slave

27:20

Byte Count–8 bits

20

Repeat start

28

Acknowledge from slave

27:21

Slave address–7 bits

36:29

Data byte 1–8 bits

28

Read = 1

37

Acknowledge from slave

29

Acknowledge from slave

45:38

Data byte 2–8 bits

37:30

Byte Count from slave–8 bits

46

Acknowledge from slave

38

Acknowledge

....

Data Byte /Slave Acknowledges

46:39

Data byte 1 from slave–8 bits

....

Data Byte N–8 bits

47

Acknowledge

....

Acknowledge from slave

55:48

Data byte 2 from slave–8 bits

....

Stop

56

Acknowledge

....

Data bytes from slave / Acknowledge

....

Data Byte N from slave–8 bits

....

NOT Acknowledge

....

Stop

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

1Start

1Start