MC145149

MOTOROLA

7

POWER SUPPLY PINS

VDD1, VDD2

Positive Power Supply (Pins 18, 13)

The most positive power supply potentials. Both of these

pins are connected to the substrate of the chip. Therefore,

both must be tied to the same voltage potential. This poten-

tial may range from 3 to 9 V with respect to the VSS pins.

For optimum performance, VDD1 should be bypassed to

VSS1 and VDD2 bypassed to VSS2. That is, two separate

bypass capacitors should be utilized.

VSS1, VSS2

Negative Power Supply (Pins 20, 11)

The most negative power supply potentials. Both of these

pins should be tied to ground.

Figure 7. Bit Stream Formats

÷ R

÷ A

÷ N

LAST BIT INTO

SHIFT REGISTER

LAST BIT INTO

SHIFT REGISTER

NOTE: The PD output state is equal to either VDD or VSS when active. When not active, the output is high

impedance and the voltage at that pin is determined by the low–pass filter capacitor.

fR

REFERENCE

(OSC

÷ R)

fV

FEEDBACK

(fin ÷ N)

PD

out

LD

Figure 8. Phase Detector/Lock Detector Output Waveforms