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HCPL0630 Datenblatt(PDF) 9 Page - Agilent(Hewlett-Packard)

Teilenummer HCPL0630
Bauteilbeschribung  Dual Channel, High CMR, High Speed, TTL Compatible Optocouplers 8 Pin DIP and SOIC-8
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Hersteller  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HCPL0630 Datenblatt(HTML) 9 Page - Agilent(Hewlett-Packard)

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9
Propagation Delay,
Pulse-Width Distortion
and Propagation Delay
Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high
(tPLH) is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low (tPHL) is
the amount of time required for
the input signal to propagate to
the output, causing the output
to change from high to low (see
Figure 7).
Pulse-width distortion (PWD)
results when tPLH and tPHL differ
in value. PWD is defined as the
difference between tPLH and tPHL
and often determines the
maximum data rate capability
of a transmission system. PWD
can be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically,
PWD on the order of 20-30% of
the minimum pulse width is
tolerable; the exact figure
depends on the particular appli-
cation (RS232, RS422, T-1, etc.).
Propagation delay skew, tPSK, is
an important parameter to
consider in parallel data appli-
cations where synchronization
of signals on parallel data lines
is a concern. If the parallel data
is being sent through a group of
optocouplers, differences in
propagation delays will cause
the data to arrive at the outputs
of the optocouplers at different
times. If this difference in
propagation delays is large
enough, it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Propagation delay skew is
defined as the difference
between the minimum and
maximum propagation delays,
either tPLH or tPHL, for any given
V
= 5.0 V
V
= 0.6 V
O
CC
6
3
-60
-20
20
60
100
T – TEMPERATURE –
°C
A
2
80
40
0
-40
0
R = 350 K
L
1
4
5
R = 1 K
L
R = 4 K
L
Insulation Related Specifications
DIP
SOIC-8
Parameter
Symbol
Value
Value
Units
Conditions
Min. External Air Gap
L(IO1)
≥7
≥4
mm
Measured from input terminals
(Clearance)
to output terminals
Min. External Tracking
L(IO2)
≥7
≥4
mm
Measured from input terminals
Path (Creepage)
to output tminals
Min. Internal Plastic
0.08
0.08
mm
Through insulation distance
Gap (Clearance)
conductor to conductor
Tracking Resistance
CTI
200
200
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
IIIa
Material group (DIN VDE 0110)
(per DIN VDE 0110)
Figure 15. Input Threshold Current
vs. Temperature.
Figure 16. Recommended Printed Circuit Board Layout.
GND BUS (BACK)
V
BUS
(FRONT)
CC
OUTPUT 1
OUTPUT 2
0.1
µF
10 mm MAX (SEE NOTE 1)


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