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ADC10D020CIVS Datenblatt(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teilenummer ADC10D020CIVS
Bauteilbeschribung  Dual 10-Bit, 20 MSPS, 150 mW A/D Converter
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Hersteller  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC10D020CIVS Datenblatt(HTML) 9 Page - National Semiconductor (TI)

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Converter Electrical Characteristics (Continued)
The following specifications apply for V
A =VD =VDR = +3.0 VDC,VREF = 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN (ac
coupled) = FSR = 1.0 V
P-P,CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS =50Ω,trc =tfc < 4 ns, NOT offset corrected.
Boldface limits apply for T
A =TMIN to TMAX: all other limits TA = 25˚C (Note 7).
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
+I
SC
Output Short Circuit Source
Current
V
OUT =0V
Parallel Mode
−7
mA
Multiplexed Mode
−14
mA
−I
SC
Output Short Circuit Sink Current
V
OUT =VDR
Parallel Mode
7
mA
Multiplexed Mode
14
mA
POWER SUPPLY CHARACTERISTICS
I
A +ID
Core Supply Current
PD = LOW, STBY = LOW, dc input
47.6
55
mA(max)
PD = LOW, STBY = HIGH
8.8
mA
PD = HIGH, STBY = LOW or HIGH
0.22
mA
I
DR
Digital Output Driver Supply
Current (Note 10)
PD = LOW, STBY = LOW, dc input
1.3
1.4
mA(max)
PD = LOW, STBY = HIGH
0.1
mA
PD = HIGH, STBY = LOW or HIGH
0.1
mA
PWR
Power Consumption
PD = LOW, STBY = LOW, dc input
150
169
mW(max)
PD = LOW, STBY = LOW, 1 MHz Input
178
mW
PD = LOW, STBY = HIGH
27
mW
PD = HIGH, STBY = LOW or HIGH
<1mW
PSRR1
Power Supply Rejection Ratio
Change in Full Scale with 2.7V to 3.6V Supply
Change
90
dB
PSRR2
Power Supply Rejection Ratio
Rejection at output with 20 MHz, 250 mV
P-P
Riding on V
A and VD
52
dB
AC Electrical Characteristics
OS = Low (Multiplexed Mode)
The following specifications apply for V
A =VD =VDR = +3.0VDC,VREF = 1.0 VDC, GAIN = OF = 0V, OS = 0V, VIN (ac
coupled) = FSR = 1.0 V
P-P,CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS =50Ω,trc =tfc < 4 ns, NOT offset corrected.
Boldface limits apply for T
A =TMIN to TMAX: all other limits TA = 25˚C (Note 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
f
CLK1
Maximum Clock Frequency
30
20
MHz(min)
f
CLK2
Minimum Clock Frequency
1
MHz
Duty Cycle
50
30
70
%(min)
%(max)
Pipeline Delay (Latency)
I Data
2.5
Clock Cycles
Q Data
3.0
Clock Cycles
t
r,tf
Output Rise and Fall Times
4
ns
t
OC
Offset Correction Pulse Width
10
ns(min)
t
OD
Output Delay from CLK Edge to
Data Valid
13
18
ns(max)
t
DIQ
I/Q Output Delay
13
ns
t
SKEW
I/Q to Data Delay
±200
ps
t
AD
Sampling (Aperture) Delay
2.4
ns
t
AJ
Aperture Jitter
<10
ps(rms)
t
VALID
Data Valid Time
21
ns
Overrange Recovery Time
Differential V
IN step from 1.5V to
0V
50
ns
t
WUPD
PD Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
<1ms
www.national.com
9


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