Datenblatt-Suchmaschine für elektronische Bauteile |
|
LM2324 Datenblatt(PDF) 9 Page - National Semiconductor (TI) |
|
|
LM2324 Datenblatt(HTML) 9 Page - National Semiconductor (TI) |
9 / 12 page 2.0 Programming Description (Continued) 2.3.4.1 Control Word Truth Table CE CNT_RST PWDN Function 1 0 0 Normal Operation 1 0 1 Synchronous Powerdown 1 1 0 Counter Reset 1 1 1 Asynchronous Powerdown 0 X X Asynchronous Powerdown Notes: X denotes don’t care. The Counter Reset enable bit when activated allows the reset of both N and R counters. Upon powering up the N counter re- sumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle). Both synchronous and asynchronous power down modes are available with the LMX2324 to be able to adapt to different types of applications. The MICROWIRE control register remains active and capable of loading and latching in data during all of the pow- erdown modes. Synchronous Power down Mode The PLL loops can be synchronously powered down by setting the counter reset mode bit to LOW (N[1] = 0) and its power down mode bit to HIGH (N[0] = 1). The power down function is gated by the charge pump. Once the power down mode and counter reset mode bits are loaded, the part will go into power down mode upon the completion of a charge pump pulse event. Asynchronous Power down Mode The PLL loops can be asynchronously powered down by setting the counter reset mode bit to HIGH (N[1] = 1) and its power down mode bit to HIGH (N[0] = 1), or by setting CE pin LOW. The power down function is NOT gated by the charge pump. Once the power down and counter reset mode bits are loaded, the part will go into power down mode immediately. The R and N counters are disabled and held at load point during the synchronous and asynchronous power down modes. This will allow a smooth acquisition of the RF signal when the PLL is programmed to power up. Upon powering up, both R and N counters will start at the ‘zero’ state, and the relationship between R and N will not be random. Serial Data Input Timing DS101030-5 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with amplitudes of 1.6V @ VCC = 2.7V and 3.3V @ VCC = 5.5V. www.national.com 9 |
Ähnliche Teilenummer - LM2324 |
|
Ähnliche Beschreibung - LM2324 |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |