Datenblatt-Suchmaschine für elektronische Bauteile |
|
SA25C512LNX Datenblatt(PDF) 11 Page - List of Unclassifed Manufacturers |
|
SA25C512LNX Datenblatt(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 19 page SA25C512 Data Sheet SAIFUN 11 Read Status Register (RDSR) The RDSR instruction provides read access to the status register. The BUSY/RDY and WREN statuses of the device can also be determined by this instruction. In addition, the Block Write Protection bits indicate the extent of protection employed. In order to determine the status of the device, the value of the /RDY bit can be continuously polled before sending any write instruction. Write Status Register (WRSR) The WRSR instruction enables the user to select one of four levels of protection. The SA25C512 is divided into four array segments. The top quarter, top half or all of the memory segments can be protected (for more details, refer to Table 7). The data within a selected segment is therefore read-only. Table 7. Block Write Protect Bits Status Register Bits Level BP1 BP0 Array Addresses Protected 0 0 0 None 1/4 0 1 C000 - FFFF 1/2 1 0 8000 - FFFF All 1 1 0000 - FFFF The WRSR instruction (as shown in Table 8) also allows the user to enable or disable the WPb pin via the WPBEN bit. Hardware write protection is enabled when the WPb pin is low and the WPBEN bit is 1, and disabled when either the WP pin is high or the WPBEN bit is 0. When the device is hardware write protected, writes to the status register are disabled. NOTE: When the WPBEN bit is hardware write protected, it cannot be changed back to 0 as long as the WPb pin is held low. Table 8. WPBEN Operation WPb WPBEN WEN Protected Blocks Un- protected Blocks Status Register X 0 0 Protected Protected Protected X 0 1 Protected Writable Writable Low 1 0 Protected Protected Protected Low 1 1 Protected Writable Protected High X 0 Protected Protected Protected High X 1 Protected Writable Writable Read Sequence (READ) Reading the SA25C512 via the SO pin requires the following sequence (for more details, see Table 9, page 12): 1. After the CSb line is pulled low to select the device, the READ opcode is transmitted via the SI line, followed by the byte address to be read. Upon completion, any data on the SI line is ignored. 2. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CSb line should be driven high after the data comes out. The READ sequence can be continued, as the byte address is automatically incremented and data continues to shift out. When the highest address is reached, the address counter rolls over to the lowest address, enabling the entire memory to be read in one continuous READ cycle. |
Ähnliche Teilenummer - SA25C512LNX |
|
Ähnliche Beschreibung - SA25C512LNX |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |