Datenblatt-Suchmaschine für elektronische Bauteile |
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ML9488 Datenblatt(PDF) 6 Page - LAPIS Semiconductor Co., Ltd. |
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ML9488 Datenblatt(HTML) 6 Page - LAPIS Semiconductor Co., Ltd. |
6 / 31 page FEDL9488-01 ML9488 6/31 I 2C interface timing (VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C) Item Symbol Condition Min. Typ. Max. Unit Applicable pin SCL clock frequency fSCL — — 400 kHz SCL Hold time (repeat) "STATRT" condition tHD,STA 0.6 — — μs SCL,SDA SCL "L" pulse width tLOW 1.3 — — μs SCL SCL "H" pulse width tHIGH 0.6 — — μs SCL Setup time for repeat "START" condition tSU,STA 0.6 — — μs SCL,SDA Data hold time tHD,DAT 0 — — ns SCL,SDA Data setup time tSU,DAT 200 — — ns SCL,SDA Setup time for "STOP" condition tSU,STO 0.6 — — μs SCL,SDA Bus free time between "STOP" condition and "START" condition tBUF 1.3 — — μs SCL Data valid acknowledge time tVD,ACK — — 1.2 μs SCL,SDAAACK Signal rise and fall time tir,tif — — (*3) μs SCL,SDA Data bus load capacitance Cb — — 400 pF SDA,SDAACK Noise pulse width tolerance twf — — 50 ns SCL,SDA (*3) tir and tif shall be reference values. The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value. Make the rise as steep as possible. Reference value: max=0.1μs. |
Ähnliche Teilenummer - ML9488 |
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Ähnliche Beschreibung - ML9488 |
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