AD5450/AD5451/AD5452/AD5453

–5–

REV. PrD

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTION

MSOP

TSOT

Mnemonic Function

18

DAC Current Output.

2

7

G N D

Ground Pin.

3

6

SCLK

Serial Clock Input. By default, data is clocked into the input shift register on the

falling edge of the serial clock input. Alternatively, by means of the serial control

bits, the device may be configured such that data is clocked into the shift register on

the rising edge of SCLK.

4

5

SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of

the serial clock input. By default, on power up, data is clocked into the shift register

on the falling edge of SCLK. The control bits allow the user to change the active

edge to rising edge.

54

SYNC

Active Low Control Input. This is the frame synchronization signal for the input

data. Data is loaded to the shift register on the active edge of the

following clocks.

63

Positive power supply input. These parts can operate from a supply of +2.5 V to

+5.5 V.

72

DAC reference voltage input pin.

81

DAC feedback resistor pin. Establish voltage output for the DAC by connecting to

external amplifier output.

PIN CONFIGURATION

AD5452/

AD5453

(Not to Scale)

IOUT1

GND

SCLK

SDIN

1

2

3

4

5

6

7

8 RFB

VREF

VDD

SYNC

AD5450/

AD5451/

AD5452/

AD5453

(Not to Scale)

IOUT1

GND

SCLK

SDIN

1

2

3

4

5

6

7

8

RFB

VREF

VDD

SYNC

MSOP (RM-8)

TSOT (UJ-8)