Datenblatt-Suchmaschine für elektronische Bauteile |
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ST25RU3993 Datenblatt(PDF) 11 Page - STMicroelectronics |
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ST25RU3993 Datenblatt(HTML) 11 Page - STMicroelectronics |
11 / 90 page DocID029764 Rev 5 11/90 ST25RU3993 Functional overview 45 The reader is enabled by setting the EN pin of the device to a positive logic level. A four-wire serial peripheral interface (SPI) is used for communication between the host system (MCU) and the reader device. The MCU is notified to service an IRQ by a logic high level on the IRQ pin. The device configuration and fine tuning of the reader performance is achieved through direct access to all control registers. The baseband data is transferred via a dual 24-byte FIFO buffer register to and from the reader device. The transmission system comprises a parallel/serial data conversion, low level data encoding and automatic generation of FrameSync, Preamble, and cyclic redundancy check (CRC). Two transmitter output ports are available: • One differential low-power, high linearity 0 dBm output that drives its power into a single ended 50 Ω load. • One differential high power output that is amplified by the internal PA. The high power output delivers up to 20 dBm and requires a single ended 50 Ω load. Both outputs are capable of amplitude shift keying (ASK) or phase reversal amplitude shift keying (PR-ASK) shaped modulation. The integrated supply voltage regulators ensure supply ripple rejection of the complete reader system. The receiver system ensures both AM and PM demodulation, and comprises a proprietary automatic gain control system. Selectable gain stages and signal bandwidth cover a wide range of input link frequencies and bit rate options. The signal strength of AM and PM modulation is measured and can be accessed through the RSSI display register (2Bh). The receiver output is selectable between digitized sub-carrier signals and internal sub-carrier decoder output. The internal decoder output delivers a bit stream and a data clock. The receiver system comprises a framing system for the baseband data. It performs a CRC check and organizes the data in bytes that are then accessible to the host system through a 24-byte FIFO register. To minimize the bill of materials (BOM), it also comprises an on-board PLL section with an integrated voltage controlled oscillator (VCO), partially integrated loop filter, supply section, ADC section and host interface section. To cover a wide range of applications the reader device has several possible configurations. The register section configures the operation and the behavior of all blocks. The device needs to be supplied via VEXT and VEXT_PA pins. The power supply connection is described in Power supply. At device power-up, the configuration registers are preset with their default values. The default values are described in the configuration register tables along with all option bits. The communication between the reader device and the transponder(s) follows the reader-talk-first method. After device power-up and register configuration, the host system (MCU) can start a communication with the transponder by turning the RF field ON and transmitting the first protocol command. Transmission and reception is possible in two modes: • Normal mode • Direct mode In normal mode the base band data is transferred through the double FIFO buffer and all protocol data processing is done internally. In the direct mode the encoders and decoders are bypassed for transmission and reception and the data processing must be done by the MCU. In the direct mode the MCU can service the analog front-end in real time. |
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Ähnliche Beschreibung - ST25RU3993 |
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