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STGIPL35K120L1 Datenblatt(PDF) 11 Page - STMicroelectronics |
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STGIPL35K120L1 Datenblatt(HTML) 11 Page - STMicroelectronics |
11 / 19 page STGIPL35K120L1 Electrical characteristics Doc ID 022751 Rev 4 11/19 3.2 Recommendations ● As the IPM may be used in a very noisy environment, care should be taken to decouple the supplies. Small ceramic capacitors, connected inside the IPM as close as possible to the gate driver pins, are used to improve noise-withstand capability. ● The IPM is compatible with both pulse transformers or optocouplers. When using an optocoupler, the IN input must be limited to approximately 5 V. The pull-up resistor to VH must be between 5 kΩ and 20 kΩ, depending on optocoupler characteristics. An optional filtering capacitor can be added in the event of a highly noisy environment, although the IPM already includes a filtering on input signals and rejects signals smaller than 100 ns (tONMIN specification). ● When using a pulse transformer, a 2.5 V reference point can be built from the 5 V VREF pin with a resistor divider. The capacitor between the VREF pin and the resistor divider middle point provides decoupling of the 2.5 V reference, and also ensures a high level on the IN input pin at power-up to start the IPM in OFF state. The waveform from the pulse transformer must comply with the tONMIN and VtON / VtOFF specifications. To turn ON the IPM outputs, the input signal must be lower than 0.8 V for at least 220 ns. Conversely, the input signal must be higher than 4.2 V for at least 200 ns to turn OFF the outputs. A pulse width of about 500 ns at these threshold levels is recommended. In all cases, the input signal at the IN pin must be between 0 and 5 V. ● To prevent the input signals oscillation, the wiring of each input should be as short as possible. ● Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. ● When setting the maximum voltage to be applied between P-N, the internal stray inductance and the maximum di/dt should be considered. Due to both internal and layout stray inductances, the di/dt results in a voltage surges between the DC-link capacitor and the switches during commutations. ● FAULT pin is externally available to provide a feedback signal about IPM status. Please refer to undervoltage protection and desaturation fault timing diagrams for more information. Fault output signals the undervoltage state and is reset only when undervoltage state disappears. When a desaturation event occurs, the fault output is pulled down and IPM outputs are low (IGBT off) until the IN input signal is released (high level), then activated again (low level). Obsolete Product(s) - Obsolete Product(s) |
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Ähnliche Beschreibung - STGIPL35K120L1 |
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