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AD1991ASVRL Datenblatt(PDF) 8 Page - Analog Devices |
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AD1991ASVRL Datenblatt(HTML) 8 Page - Analog Devices |
8 / 11 page REV. 0 –8– AD1991 APPLICATION CONSIDERATIONS Good board layout and decoupling are vital for correct operation of the AD1991. Due to the fact that the part switches high currents, there is the potential for large PVDD bounce each time a transis- tor transitions. This can cause unpredictable operation of the part. To avoid this potential problem, close chip decoupling is essen- tial. It is also recommended that the decoupling capacitors be placed on the same side of the board as the AD1991 and connected directly to the PVDD and PGND pins. By placing the decoupling capacitors on the other side of the board and decoupling through vias, the effectiveness of the decoupling is reduced. This is because vias have inductive properties and, therefore, prevent very fast discharge of the decoupling capacitors. Best operation is achieved with at least one decoupling capacitor on each side of the AD1991 or optionally two capacitors per side can be used to further reduce the series resistance of the capacitor. If these decoupling recommendations cannot be followed and decoupling through vias is the only option, the vias should be made as large as possible to increase surface area, thereby reducing inductance and resistance. Figures 5 and 6 show two possible layouts to provide close chip decoupling. In both cases, the PVDD to PGND decoupling is as close as possible to the pins of the AD1991. One solution uses surface-mount capacitors that offer low inductance; however, each output (OUTA, OUTB, OUTC, and OUTD) must be brought through vias to another layer of the board to be brought to the LC filter. The other solution uses through-hole capacitors that have higher inductance but allow the outputs to connect directly to the LC filter. In this solution, the inductor for OUTA and OUTC would span the PVDD trace. These diagrams show four decoupling capacitors from PVDD to PGND; however, this may not be necessary if capacitors with low series resistance are used. Another close chip capacitor is used for AVDD to AGND decoupling, with the actual power connections to the capacitors being done through vias. This is quite acceptable since AVDD is a low current stable supply. Finally, a close chip capacitor is used to decouple DVDD to DGND. This is quite important since DVDD is a digital supply whose current will change dynamically and, therefore, requires good decoupling. For both PVDD and DVDD, additional reservoir capacitors should be used to augment the close chip decoupling, especially for PVDD, which usually has very large transients. THERMAL CONSIDERATIONS Careful consideration must be given to heat sinking the AD1991, particularly in applications where the ambient temperature can be much higher than normal room temperature. The three thermal resistances of JC, CA, and JA should be known in order to correctly heat sink the part. These values specify the temperature difference between two points, per unit power dissipation. JC specifies the temperature difference between the junction (die) and the case (package) for each watt of power dissipated in the die. The AD1991 is specified with a JC of 1 °C/W, which means that for each watt of power dissipated in the part, the junction (or die) temperature will be 1ºC higher than the case (or package) temperature. The value of CA, the difference between the case and ambient temperatures, is entirely dependent on the size of heat sink attached to the case, the material used, the method of attach- ment, and the airflow over the heat sink. The value of CA is specified as 26 °C/W for no heat sink and no airflow over the device. Finally, JA is the sum of the JC and CA values, and will be between 1 °C/W and 27°C/W depending on the heat sink used. This is the temperature difference between the junction (die) and ambient temperature around the case (package) for each watt dissipated in the part. The AD1991 is specified to have a thermal shutdown of typically 150 °C die temperature. Good design procedures allow for a margin, so the system should be designed such that the AD1991 die never goes above 140 °C. Knowing the maximum desirable die temperature, the efficiency of the AD1991, the maximum ambient temperature, and the maximum power that will be delivered to the load, the necessary CA can be calculated. For an 8 Ω load, the AD1991 has a typical efficiency of 87%, which can be reduced slightly to be conservative. For this example, assume an 85% efficiency. If the power delivered to the loads is to be 2 20 W rms continuous power, the power dissipated in the AD1991 can be calculated as follows: Power Supplied to Loads = 40 W rms Total Power Supplied to the AD1991 = (40/85 100) = 47 W rms Power Dissipated in the AD1991 = 7 W rms If the ambient temperature can reach 85 °C maximum, the allowable difference between the die temperature and ambient temperature is (140 – 85) = 55 °C. This gives a JA requirement of (55/7) = 7.9 °C/W. This requires a heat sink that gives a CA of 6.9 °C/W. The size and type of heat sink required can now be calculated. If adequate heat sinking is not applied to the AD1991, the system will suffer from the AD1991 going into thermal shutdown. It is advisable to also use the thermal warning output on the AD1991 to attenuate the power being delivered to help prevent thermal shutdown. POWER-UP CONSIDERATIONS Careful power-up is necessary when using the AD1991 to ensure correct operation and to avoid possible latch-up issues. The AD1991 should be held in RESET with MUTEB asserted until all three power supplies have stabilized. Once the supplies have stabilized, the part can be brought out of RESET, and following this, MUTEB can be negated. |
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