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ACE25AC200G Datenblatt(PDF) 7 Page - ACE Technology Co., LTD. |
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ACE25AC200G Datenblatt(HTML) 7 Page - ACE Technology Co., LTD. |
7 / 24 page ACE25AC200G SPI NOR FLASH VER 1.2 7 Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low→Send Write Enable command→CS# goes high. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low Send Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Read Status Register (RDSR) (05H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. Figure1. Write Enable Sequence Diagram Figure2. Write Disable Sequence Diagram Figure3. Read Status Register Sequence Diagram |
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