LM25145 datasheet(5/62 Pages) TI1

Teilenummer	LM25145

Bauteilbeschribung	6-V to 42-V Synchronous Buck DC-DC Controller With Wide Duty Cycle Range

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LM25145

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SNVSAT9 – JUNE 2017

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Pin Functions (continued)

TYPE(1)

DESCRIPTION

NO.

NAME

6

AGND

P

Analog ground. Return for the internal 0.8-V voltage reference and analog circuits.

7

SYNCOUT

O

Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-

side FET gate drive. Connect SYNCOUT of the master LM25145 to the SYNCIN pin of a second LM25145

to operate two controllers at the same frequency with 180° interleaved high-side FET switch turnon

transitions. Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating

from an external clock that is different from the free-running frequency set by the RT resistor.

8

SYNCIN

I

Dual function pin for providing an optional clock input and for enabling diode emulation by the low-side

MOSFET. Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode

emulation by the low-side MOSFET is disabled when the controller is synchronized to an external clock,

and negative inductor current can flow in the low-side MOSFET with light loads. A continuous logic low

state at the SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode

emulation results in DCM operation at light loads, which improves efficiency. A logic high state at the

SYNCIN pin disables diode emulation producing forced-PWM (FPWM) operation. During soft-start when

SYNCIN is high or a clock signal is present, the LM25145 operates in diode emulation mode until the

output is in regulation, then gradually increases the SW zero-cross threshold, resulting in a gradual

transition from DCM to FPWM.

9

NC

—

No electrical connection.

10

PGOOD

O

Power Good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin

is within a specified tolerance window centered at 0.8 V.

11

ILIM

I

Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an

external resistor programs the threshold voltage for valley current limiting. The opposite end of the

threshold adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing

or to a current sense resistor connected to the source of the low-side FET.

12

PGND

P

Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-

side MOSFET or the ground side of a shunt resistor.

13

LO

P

Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through

a short, low inductance path.

14

VCC

O

Output of the 7.5-V bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as

close to the controller as possible. Controller bias can be supplied from an external supply that is greater

than the internal VCC regulation voltage. Use caution when applying external bias to ensure that the

applied voltage is not greater than the minimum VIN voltage and does not exceed the VCC pin maximum

operating rating, see Recommended Operating Conditions.

15

EP

—

Pin internally connected to exposed pad of the package. Electrically isolated.

16

NC

—

No electrical connection.

17

BST

O

Bootstrap supply for the high-side gate driver. Connect to the bootstrap capacitor. The bootstrap capacitor

supplies current to the high-side FET gate and should be placed as close to controller as possible. If an

external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the

cathode of the diode to the BST pin and anode to VCC.

18

HO

P

High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low

inductance path.

19

SW

P

Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-

side MOSFET and the drain terminal of the low-side MOSFET using short, low inductance paths.

20

VIN

P

Supply voltage input for the VCC LDO regulator.

—

EP

—

Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal

resistance.

6.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high

reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins

and terminals that are easily viewed. It is therefore difficult to determine visually whether or not the package is

successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve

the issue of side-lead wetting of leadless packaging. The LM25145 is assembled using a 20-pin VQFN package

with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and

manufacturing costs.

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