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CS4399 Datenblatt(PDF) 11 Page - Cirrus Logic

Teilenummer CS4399
Bauteilbeschribung  130-dB, 32-Bit High-Performance DAC
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

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DS1113F1
11
CS4399
3 Characteristics and Specifications
3 Characteristics and Specifications
Table 3-1 defines parameters as they are characterized in this section.
Table 3-1. Parameter Definitions
Parameter
Definition
Dynamic range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. A
signal-to-noise ratio measurement over the specified bandwidth made with a –60-dB signal; 60 dB is added to resulting
measurement to refer the measurement to full scale. This technique ensures that distortion components are below the
noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering
Society, AES17–1991, and the Electronic Industries Association of Japan, EIAJ CP–307. Dynamic range is expressed in
decibel units.
Gain drift
The change in gain value with temperature, expressed in ppm/°C units.
Idle channel noise The rms value of the signal with no input applied (properly back-terminated analog input, digital zero, or zero modulation
input). Measured over the specified bandwidth.
Interchannel gain
mismatch
The gain difference between left and right channel pairs. Interchannel gain mismatch is expressed in decibel units.
Interchannel
phase mismatch
The phase difference between left and right channel pairs at 997-Hz sine wave input. Interchannel phase mismatch is ex-
pressed in degree units (with respect to 997-Hz sine wave input).
Interchannel
isolation
A measure of cross talk between the left and right channel pairs. Interchannel isolation is measured for each channel at
the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Interchannel
isolation is expressed in decibel units.
Load resistance
and capacitance
The recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal
integrity. The load capacitance effectively moves the band-limiting pole of the amp in the output stage. Increasing load ca-
pacitance beyond the recommended value can cause the internal op-amp to become unstable.
Output offset
voltage
The DC offset voltage present at the amplifier’s output when its input signal is in a mute state. The offset exists due to
CMOS process limitations and is proportional to analog volume settings. When measuring the offset out of the headphone
amplifier, the headphone amplifier is ON.
Total harmonic
distortion + noise
(THD+N)
The ratio of the rms sum of distortion and noise spectral components across the specified bandwidth (typically 20 Hz–20
kHz) relative to the rms value of the signal. THD+N is measured at –1 and –20 dBFS for the analog input and at 0 and
–20 dB for the analog output, as suggested in AES17–1991 Annex A. THD+N is expressed in decibel units.
Turn-on time
Turn-on time is measured from when the PDN_HP = 0 ACK signal is received to when the signal appears on the HP output.
Table 3-2. Recommended Operating Conditions
GNDD = GNDA = 0 V, all voltages with respect to ground.
Parameters 1
1.Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of
these limits may adversely affect device reliability.
Symbol
Minimum
Maximum
Units
DC power supply
Analog
VA
1.66
1.94
V
Charge pump
VCP
1.66
1.94
V
Filtered charge pump
EXT_VCPFLT = 1 VCP_FILT+
2.85
3.15
V
VCP_FILT–
–3.15
–2.85
V
Battery supply
HV_EN = 0, EXT_VCPFILT = 0
HV_EN = 1, EXT_VCPFILT = 0
EXT_VCPFILT = 1
VP
3.0
3.3
3.3
5.25
5.25
5.25
V
V
V
Digital Interface
VL
1.66
1.94
V
Digital Internal
VD
1.66
1.94
V
External voltage
applied to pin2,3
2.The maximum over/undervoltage is limited by the input current.
3.Table 1-1 lists the power supply domain in which each CS4399 pin resides.
HP_DETECT pin
VCP_FILT± domain pins 4
VL domain pins
VA domain pins
VP domain pins
4.VCP_FILT± is specified in Table 3-13.
VINHI
VVCPF
VVL
VVA
VVP
–0.3 – VCP_FILT–
–0.3 – VCP_FILT–
–0.3
–0.3
–0.3
VP + 0.3
0.3 + VCP_FILT+
VL + 0.3
VA + 0.3
VP + 0.3
V
V
V
V
V
Ambient temperature
TA
–10
+70
C


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