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ST16C2552IJ44 Datenblatt(PDF) 8 Page - Exar Corporation |
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ST16C2552IJ44 Datenblatt(HTML) 8 Page - Exar Corporation |
8 / 28 page 3-142 ST16C2552 *RECEIVE TIME-OUT: This mode is enabled when STARTECH UART is operating in FIFO mode. Receive time out will not occur if the receive FIFO is empty. The time out counter will be reset at the center of each stop bit received or each time receive holding register is read. The actual time out value is T ( Time out length in bits)= 4 X P ( Programmed word length) + 12. To convert time out value to a character value, user has to divide this number to its complete word length + parity ( if used) + number of stop bits and start bit. Example -A: If user programs the word length = 7, and no parity and one stop bit, Time out will be: T = 4 X 7( programmed word length) +12 = 40 bits Character time = 40 / 9 [ (programmed word length = 7) + (stop bit = 1) + (start bit = 1)] = 4.4 characters. Example -B: If user programs the word length = 7, with parity and one stop bit, the time out will be: T = 4 X 7(programmed word length) + 12 = 40 bits Character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. ISR BIT-0: 0=an interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. 1=no interrupt pending. ISR BIT 1-3: Logical combination of these bits, provides the high- est priority interrupt pending. ISR BIT 4-7: These bits are not used and are set to zero if the FIFOs are not enabled.BIT 6-7: are set to “1” when the FIFOs are enabled. FIFO CONTROL REGISTER (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receiver FIFO trigger level, and select the type of DMA signaling. FCR BIT-0: 0=Disable the transmit and receive FIFO. 1=Enable the transmit and receive FIFO. IER BIT-1: 0=disable the transmitter empty interrupt. 1=enable the transmitter empty interrupt. IER BIT-2: 0=disable the receiver line status interrupt. 1=enable the receiver line status interrupt. IER BIT-3: 0=disable the modem status register interrupt. 1=enable the modem status register interrupt. IER BIT 4-7: All these bits are set to logic zero. INTERRUPT STATUS REGISTER (ISR) The ST16C2552 provides four level prioritized inter- rupt conditions to minimize software overhead during data character transfers. The Interrupt Status Regis- ter (ISR) provides the source of the interrupt in priori- tized matter. During the read cycle the ST16C2552 provides the highest interrupt level to be serviced by CPU. No other interrupts are acknowledged until the particular interrupt is serviced. The following are the prioritized interrupt levels: Priority level P D3 D2 D1 D0 Source of the interrupt 1011 0 LSR (Receiver Line Sta- tus Register) 2010 0 RXRDY (Received Data Ready) 2* 1 1 0 0 RXRDY (Receive Data time out) 3001 0 TXRDY( Transmitter Holding Register Empty) 4000 0 MSR (Modem Status Register) |
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