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GS81314PD18GK-133 Datenblatt(PDF) 10 Page - GSI Technology |
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GS81314PD18GK-133 Datenblatt(HTML) 10 Page - GSI Technology |
10 / 39 page GS81314PD18/36GK-133/120/106 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.09 5/2016 10/39 © 2014, GSI Technology Post Input Training Requirements In this case, MRW is driven asynchronously, whereas R, W, and SA[10:1] are all driven synchronously (i.e. they all meet setup and hold time specs to CK). When Register Write Mode is utilized in this manner, multiple registers can be programmed during any particular instance that MRW is asserted High. The timing diagrams below arbitrarily show four registers programmed while MRW is asserted High, but in practice it can be any number greater than or equal to one. The requirements for this usage case are as follows: • At least 16 NOPs must be initiated before and after the Register Write(s). • MRW High must meet minimum setup time requirements (tMRWS) to the CK that generates the first Register Write. • MRW High must meet minimum hold time requirements (tMRWH) from the CK that generates the first NOP after the last Reg- ister Write. • R must be driven Low (synchronously) and SA[10:1] must be driven Valid (synchronously) for each Register Write. • W state is a “don’t care” (synchronously) for each Register Write. Note: tMRWS = tMRWH = 4 cycles (minimum). Asynchronous Register Write Timing Diagram - Pre Input Training tMRWH CK W SA[10:1] Register Write Mode Register #n MRW tMRWS tMRWPW R Must be “high” to prevent memory write; “don’t care” otherwise 16 NOPs 16 NOPs Asynchronous Register Write Timing Diagram - Post Input Training CK SA[10:1] W Register Write Mode 16 NOPs Read / Write Read / Write 16 NOPs Reg #d Reg #a MRW Reg #b Reg #c tIVKH tKHIX R tMRWH tMRWS X X X X V VV V V V V V V |
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