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GS81314PQ18GK-133I Datenblatt(PDF) 7 Page - GSI Technology |
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GS81314PQ18GK-133I Datenblatt(HTML) 7 Page - GSI Technology |
7 / 39 page GS81314PQ18/36GK-133/120/106 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.09 5/2016 7/39 © 2014, GSI Technology Power-Up and Reset Requirements For reliability purposes, power supplies must power up simultaneously, or in the following sequence: VSS, VDD, VDDQ, VREF and inputs. Power supplies must power down simultaneously, or in the reverse sequence. After power supplies power up, the following start-up sequence must be followed. Step 1: Assert RST High for at least 1ms. While RST is asserted high: • The PLL is disabled. • The states of R, W, and MRW control inputs are ignored. Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM. Step 2: Begin toggling input clocks. After input clocks begin toggling, but not necessarily within specification: • Q are placed in the non-Read state, and remain so until the first Read operation. • QVLD are driven Low, and remain so until the first Read operation. • CQ, CQ begin toggling, but not necessarily within specification. Step 3: Wait until input clocks are stable and toggling within specification. Step 4: De-assert RST Low. Step 5: Wait at least 384K (393,216) cycles. During this time: • Driver and ODT impedances are calibrated. Can take up to 320K cycles. • The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles. Step 6: Enable the PLL. Step 7: Wait at least 64K (65,536) cycles for the PLL to lock. After the PLL has locked: • CQ, CQ begin toggling within specification. Step 8: Continue initialization (see the Initialization Flow Chart). Reset Usage Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted Low, as in step 4 above, steps 5~7 above must be followed before normal operation is resumed. It is up the system to determine whether further re-initialization beyond step 7 (as outlined in the Initialization Flow Chart) is required before normal operation is resumed. Note: Memory array content may be perturbed/corrupted when RST is asserted High. |
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