Datenblatt-Suchmaschine für elektronische Bauteile |
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GS8182D37BD-300 Datenblatt(PDF) 6 Page - GSI Technology |
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GS8182D37BD-300 Datenblatt(HTML) 6 Page - GSI Technology |
6 / 27 page GS8182D19/37BD-435/400/375/333/300 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03a 11/2011 6/27 © 2008, GSI Technology Power-Up Sequence for SigmaQuad-II+ SRAMs For compatibility across all vendors it is recommended that SigmaQuad-II+ SRAMs be powered-up in a specific sequence in order to avoid unde- fined operations Power-Up Sequence 1. Power-up and maintain Doff at low state. 1a. Apply VDD. 1b. Apply VDDQ. 1c. Apply VREF (may also be applied at the same time as VDDQ). 2. After voltages are within specification range, and clocks (K, K) are stablized, change Doff to high. 3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled. Note: The DLL may be reset by driving the Doff pin low or by stopping the K clocks for at least 30ns. 2048 cycles of clean K clocks are always required to re-lock the DLL after reset. DLL Constraints The DLL synchronizes to either K clock. These clocks should have low phase jitter (tKCVar). • The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired operating clock frequency. • If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage. Special Functions Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time BW0 BW1 D0–D8 D9–D17 Beat 1 0 1 Data In Don’t Care Beat 2 1 0 Don’t Care Data In Beat 3 0 0 Data In Data In Beat 4 1 0 Don’t Care Data In Resulting Write Operation Byte 1 D0–D8 Byte 2 D9–D17 Byte 1 D0–D8 Byte 2 D9–D17 Byte 1 D0–D8 Byte 2 D9–D17 Byte 1 D0–D8 Byte 2 D9–D17 Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1 Beat 2 Beat 3 Beat 4 |
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