Datenblatt-Suchmaschine für elektronische Bauteile |
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RT5508 Datenblatt(PDF) 49 Page - Richtek Technology Corporation |
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RT5508 Datenblatt(HTML) 49 Page - Richtek Technology Corporation |
49 / 57 page RT5508 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5508-01 March 2017 www.richtek.com 49 ADDR Byte Bits R/W Name Description Default 0xA4 3 23:0 R/W nDelay[23:0] The delay added to the output voltage of SPKFB for synchronization. nDelay = reg[0xa4] / 2^21 The range is [-2, 3) with 21 fractional bits. 0 0xA5 3 23:0 R/W res[23:0] The initial value of the parameter which is propotional to the resistance. Resistance = reg[0xa5] / 2^23 The range is [0, 2) with 23 fractional bits. 24'h800000 0xA6 3 23:0 R/W phi1[23:0] The initial value of the radians for the adaptive filter. The radians π/2 is normalized to 1/2, and the range is [-0.5, 0.5] with 23 fractional bits. Phi1 = reg[a6] / 2^23 * pi 24'hC4266F 0xA7 3 23:0 R/W phi2[23:0] 24'h345F58 0xA8 3 23:0 R/W phi3[23:0] 24'hFE21CB 0xA9 3 23:0 R/W phi4[23:0] 24'h000000 0xAA 3 23:0 R/W phi5[23:0] 24'h000000 0xAB 3 23:0 R/W Adptive_b0[23:0] The initial value of the expansion coefficient for the adaptive filter. The range is [-2, 2) with 22 fractional bits. B0 = reg[ab] / 2^22 24'h10221 0xAC 3 23:0 R/W Adptive_b1[23:0] 24'hF1EBC8 0xAD 3 23:0 R/W Adptive_b2[23:0] 24'h33BD58 0xAE 3 23:0 R/W Adptive_b3[23:0] 24'h309E9 0xAF 3 23:0 R/W Adptive_b4[23:0] 24'h000000 0xB0 3 23:0 R/W Adptive_b5[23:0] 24'h000000 0xB3 1 7:5 - Reserved - 4:3 R/W selMinAtc The minimum value of the ATC gain 0 : 1/16 1 : 1/8 2 : 1/4 3 : 1/2 2'b0 2 R/W disMinAtc Disable the minimum limitation of the ATC gain 1'b0 1 R/W D_VBG_PLDO_ON 1'b0 0 R/W R_AD_DITH_EN Current sense ADC dither enable 1'b0 0xB4 1 7 R/W OTP_PLL_LOCK_IGNORE Access MTP memory without PLL lock 0 6:4 - Reserved - 3 R/W TDM_EN I 2S TDM enable bit 0 2 R/W TDM_ADC_SEL I 2S ADC TDM slot selection 0 1 R/W TDM_DAC_SEL I 2S DAC TDM slot selection 0 0 R/W dcrEstInSilMod Do DCR estimation when act signal is not logic 0 0 |
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