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CD74HC299M96E4 Datenblatt(PDF) 1 Page - Texas Instruments |
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CD74HC299M96E4 Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 15 page 1 Data sheet acquired from Harris Semiconductor SCHS178C Features • Buffered Inputs • Four Operating Modes: Shift Left, Shift Right, Load and Store • Can be Cascaded for N-Bit Word Lengths • I/O0 - I/O7 Bus Drive Capability and Three-State for Bus Oriented Applications • Typical fMAX = 50MHz at VCC =5V, CL = 15pF, TA =25 oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD54HC299, CD54HCT299 (CERDIP) CD74HC299, CD74HCT299 (PDIP, SOIC) TOP VIEW Description The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 - I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be stable one set- up time prior to the clock positive transition. The Master Reset (MR) is an asynchronous active low input. When MR output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage. The three-state input/output I(/O) port has three modes of operation: 1. Both output enable (OE1 and OE2) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs. 2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready for par- allel data to be loaded into eight registers with one clock transition regardless of the status of OE1 and OE2. 3. Either one of the two output enable inputs being high will force I/O terminals to be in the off-state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 S0 OE1 OE2 I/O6 I/O4 I/O2 Q0 I/O0 MR GND VCC DS7 Q7 I/O7 S1 I/O5 I/O3 I/O1 CP DS0 Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE CD54HC299F3A -55 to 125 20 Ld CERDIP CD54HCT299F3A -55 to 125 20 Ld CERDIP CD74HC299E -55 to 125 20 Ld PDIP CD74HC299M -55 to 125 20 Ld SOIC CD74HC299M96 -55 to 125 20 Ld SOIC CD74HCT299E -55 to 125 20 Ld PDIP CD74HCT299M -55 to 125 20 Ld SOIC CD74HCT299M96 -55 to 125 20 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. January 1998 - Revised May 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State [ /Title (CD74 HC299 , CD74 HCT29 9) /Sub- ject (High Speed CMOS Logic 8-Bit Uni- versal Shift |
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