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ES4228 Datenblatt(PDF) 3 Page - List of Unclassifed Manufacturers

Teilenummer ES4228
Bauteilbeschribung  Internet Set-Top Box Solution
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ES4228 Datenblatt(HTML) 3 Page - List of Unclassifed Manufacturers

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ESS Technology, Inc.
SAM0378-053001
3
ES4228/ES4227 PRODUCT BRIEF
ES4228 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES4228.
Table 1
ES4228 Pin Descriptions List
Name
Number
I/O
Description
VCC
1, 9, 18, 27, 35, 44, 51, 59,
68, 75, 83, 92, 99, 104, 111,
121, 130, 139, 148, 157,
164, 172, 183, 193, 201
I
3.45 V power supply.
LA[21:0]
23:19, 16:10, 7:2, 207:204
O
Device address output.
VSS
8, 17, 26, 34, 43, 52, 60,
67, 76, 84, 91, 98, 103, 112,
120, 129, 138, 147, 156,
163, 171, 177, 184, 192,
200, 208
I
Ground.
RESET#
24
I
Reset input, active low.
TDMDX
25
O
TDM transmit data.
RSEL
I
ROM Select.
TDMDR
28
I
TDM receive data.
TDMCLK
29
I
TDM clock input.
TDMFS
30
I
TDM frame sync.
TDMTSC#
31
O
TDM output enable, active low.
TWS
32
O
Audio transmit frame sync.
SEL_PLL1
I
Refer to the description and matrix for SEL_PLL0 pin 33.
TSD
33
O
Audio transmit serial data port.
SEL_PLL0
I
System and DSCK output clock frequency selection at reset time. The matrix
below lists the available clock frequencies and their respecitve PLL bit
settings.
SEL_PLL2
36
I
Refer to the description and matrix for SEL_PLL0 pin 33.
MCLK
39
I/O
Audio master clock for audio DAC.
TBCK
40
I/O
Audio transmit bit clock.
RSD
45
I
Audio receive serial data.
RWS
46
I
Audio receive frame sync.
RBCK
47
I
Audio receive bit clock.
APLLCAP
48
I
Analog PLL Capacitor.
XIN
49
I
Crystal input.
XOUT
50
O
Crystal output.
RSEL
Selection
0
8-bit ROM
1
16-bit ROM
SEL_PLL2
SEL_PLL1 SEL_PLL0 Clock Output
00
0
VCO doesn’t work.
0
0
1
27 MHz
0
1
0
Bypass mode
0
1
1
54 MHz
1
0
0
121.5 MHz
1
0
1
81 MHz
1
1
0
94.5 MHz
1
1
1
108 MHz


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