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SN74AUP1G125DRL Datenblatt(PDF) 2 Page - Texas Instruments

Teilenummer SN74AUP1G125DRL
Bauteilbeschribung  Low-Power Single Bus Buffer Gate With 3-State Output
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SN74AUP1G125DRL Datenblatt(HTML) 2 Page - Texas Instruments

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SN74AUP1G125
SCES595N – JULY 2004 – REVISED JULY 2017
www.ti.com
Product Folder Links: SN74AUP1G125
Submit Documentation Feedback
Copyright © 2004–2017, Texas Instruments Incorporated
Table of Contents
1
Features .................................................................. 1
2
Applications ........................................................... 1
3
Description ............................................................. 1
4
Revision History..................................................... 2
5
Pin Configuration and Functions ......................... 3
6
Specifications......................................................... 4
6.1
Absolute Maximum Ratings ...................................... 4
6.2
ESD Ratings.............................................................. 4
6.3
Recommended Operating Conditions ....................... 5
6.4
Thermal Information .................................................. 5
6.5
Electrical Characteristics, TA = 25°C ........................ 6
6.6
Electrical Characteristics, TA = –40°C to +85°C ....... 7
6.7
Switching Characteristics, CL = 5 pF ........................ 8
6.8
Switching Characteristics, CL = 10 pF ...................... 9
6.9
Switching Characteristics, CL = 15 pF .................... 10
6.10
Switching Characteristics, CL = 30 pF .................. 11
6.11
Operating Characteristics...................................... 12
6.12
Typical Characteristics .......................................... 12
7
Parameter Measurement Information ................ 13
8
Detailed Description ............................................ 15
8.1
Overview ................................................................. 15
8.2
Functional Block Diagram ....................................... 15
8.3
Feature Description................................................. 15
8.4
Device Functional Modes........................................ 16
9
Application and Implementation ........................ 17
9.1
Application Information............................................ 17
9.2
Typical Application .................................................. 17
10
Power Supply Recommendations ..................... 18
11
Layout................................................................... 18
11.1
Layout Guidelines ................................................. 18
11.2
Layout Example .................................................... 18
12
Device and Documentation Support ................. 20
12.1
Documentation Support ........................................ 20
12.2
Receiving Notification of Documentation Updates 20
12.3
Community Resources.......................................... 20
12.4
Trademarks ........................................................... 20
12.5
Electrostatic Discharge Caution ............................ 20
12.6
Glossary ................................................................ 20
13
Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (December 2015) to Revision N
Page
Added DPW (X2SON) package.............................................................................................................................................. 1
Deleted Device Comparison table, see Mechanical, Packaging, and Orderable Information section at the end of the
data sheet ............................................................................................................................................................................... 1
Changed Simplified Schematic with a new schematic ........................................................................................................... 1
Added column for X2SON (DPW) package and separated columns for DSBGA packages in Pin Functions table .............. 3
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5
Added Balanced High-Drive CMOS Push-Pull Outputs, Standard CMOS Inputs, Clamp Diodes, Partial Power Down
(Ioff), and Over-voltage Tolerant Inputs................................................................................................................................. 15
Added Trace Example and revised Layout Guidelines ........................................................................................................ 18
Added Receiving Notification of Documentation Updates section ....................................................................................... 20
Changes from Revision L (February 2013) to Revision M
Page
Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
Changes from Revision K (November 2012) to Revision L
Page
Changed Y to Y for pin 4 in DSF Package pin out ................................................................................................................ 3


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